Specifications
Table 65: I OUTPUT connector pin assignment (cont.)
Pin number Signal name Description
20 EXT_I14–
45 EXT_I14+
I output data (bit 14), LVDS
21 EXT_I15–
46 EXT_I15+
I output data (bit 15), LVDS
22
GND
47
GND
23
GND
48
GND
Ground
24
EXT_IQ_DAV–
49
EXT_IQ_DAV+
IQ Data Valid indic a tor, LVDS
25
EXT_IQ_CLK–
50
EXT_IQ_CLK+
IQ output clock, LVDS
Table 66: Q OUTPUT connector pin assignment
Pin number Signal name Description
1
IQ_ENABLE* IQ output enable signal input
Open: IQ output disable
GND: IQ output enable
26
GND
2
GND
27
GND
Ground
3
EXT_Q0–
28
EXT_Q0+
Q output data (bit 0), LVDS
4
EXT_Q1–
29
EXT_Q1+
Q output data (bit 1), LVDS
5
EXT_Q2–
30
EXT_Q2+
Q output data (bit 2), LVDS
6
EXT_Q3–
31
EXT_Q3+
Q output data (bit 3), LVDS
7
GND
32
GND
Ground
8
EXT_Q4–
33
EXT_Q4+
Q output data (bit 4), LVDS
9
EXT_Q5–
34
EXT_Q5+
Q output data (bit 5), LVDS
10
EXT_Q6–
35
EXT_Q6+
Q output data (bit 6), LVDS
66 RSA5100B Series Technical Reference