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Clock Outputs (DCLKout and SDCLKout)
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SNAU145B–MAY 2013–Revised March 2018
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Typical Phase Noise Performance Plots
Figure 24. LMK04828 DCLKout2, VCO0, 245.76 MHz, Div10, LVPECL20 /w
240-Ω Emitter Resistor, DCLKoutX_MUX=Divider, IDL=1, ODL=0, Balun = ADT2-1T
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