Texas Instruments LMK04828 User Manual

DAC
Recovered
³GLUW\´FORFNRU
clean clock
0XOWLSOH³FOHDQ´
clocks at different
frequencies
DCLKout0 &
DCLKout2
DCLKout12
DCLKout4,
SDCLKout5
FPGA
CLKin0
Crystal or
VCXO
Backup
Reference
Clock
CLKin1
OSCout
DAC
SDCLKout1 &
SDCLKout3
ADC
LMX2581
PLL+VCO
Serializer/
Deserializer
LMK0482xB
SDCLKout13
SDCLKout9 &
SDCLKout11
DCLKout8 &
DCLKout10
Product
Folder
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Buy
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LMK04821 , LMK04826 , LMK04828
SNAS605AR –MARCH 2013–REVISED DECEMBER 2015
LMK0482x Ultra Low-Noise JESD204B Compliant
Clock Jitter Cleaner with Dual Loop PLLs
1 Features 2 Applications
1
• JEDEC JESD204B Support
• Wireless Infrastructure
• Ultra-Low RMS Jitter • Data Converter Clocking
• Networking, SONET/SDH, DSLAM
– 88 fs RMS Jitter (12 kHz to 20 MHz)
• Medical / Video / Military / Aerospace
– 91 fs RMS Jitter (100 Hz to 20 MHz)
• Test and Measurement
– –162.5 dBc/Hz Noise Floor at 245.76 MHz
• Up to 14 Differential Device Clocks from PLL2
3 Description
– Up to 7 SYSREF Clocks
The LMK0482x family is the industry's highest
– Maximum Clock Output Frequency 3.1 GHz
performance clock conditioner with JEDEC
– LVPECL, LVDS, HSDS, LCPECL
JESD204B support.
Programmable Outputs from PLL2
The 14 clock outputs from PLL2 can be configured to
• Up to 1 Buffered VCXO/Crystal Output from PLL1
drive seven JESD204B converters or other logic
devices using device and SYSREF clocks. SYSREF
– LVPECL, LVDS, 2xLVCMOS Programmable
can be provided using both DC and AC coupling. Not
• Dual Loop PLLatinum™ PLL Architecture
limited to JESD204B applications, each of the 14
• PLL1
outputs can be individually configured as high
– Up to 3 Redundant Input Clocks
performance outputs for traditional clocking systems.
– Automatic and Manual Switch-Over Modes
The high performance combined with features like the
ability to trade off between power or performance,
– Hitless Switching and LOS
dual VCOs, dynamic digital delay, holdover, and
– Integrated Low-Noise Crystal Oscillator Circuit
glitchless analog delay make the LMK0482x family
– Holdover mode when Input Clocks are Lost
ideal for providing flexible high performance clocking
• PLL2
trees.
– Normalized [1 Hz] PLL Noise Floor of
Device Information
(1)
-227 dBc/Hz
PART VCO0
VCO1 FREQUENCY
– Phase Detector Rate up to 155 MHz
NUMBER FREQUENCY
– OSCin Frequency-Doubler
2920 to 3080 MHz
LMK04821 1930 to 2075 MHz VCO1 Div = ÷2 to ÷8
– Two Integrated Low-Noise VCOs
(÷2 = 1460 to 1540 MHz)
• 50% Duty Cycle Output Divides, 1 to 32
LMK04826B 1840 to 1970 MHz 2440 to 2505 MHz
(even and odd)
LMK04828B 2370 to 2630 MHz 2920 to 3080 MHz
• Precision Digital Delay, Dynamically Adjustable
(1) For all available packages, see the orderable addendum at
• 25 ps Step Analog Delay
the end of the datasheet.
• Multi-mode: Dual PLL, single PLL, and Clock
Simplified Schematic
Distribution
• Industrial Temperature Range: –40 to 85°C
• Supports 105°C PCB Temperature (Measured at
Thermal Pad)
• 3.15-V to 3.45-V Operation
• Package: 64-Pin QFN (9.0 mm x 9.0 mm x 0.8
mm)
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.

Texas Instruments LMK04828 Specifications

General

Brand	Texas Instruments
Model	LMK04828
Category	Motherboard
Language	English

Summary

Features

Ultra-Low RMS Jitter

Specifies the ultra-low RMS jitter performance of the device.

Dual Loop PLLatinum PLL Architecture

Details the dual loop PLL architecture for improved performance.

Applications

Wireless Infrastructure

Lists wireless infrastructure as a key application area.

Data Converter Clocking

Highlights data converter clocking as a primary application.

Description

LMK0482x Family Overview

Provides an overview of the LMK0482x family of clock conditioners.

Device Comparison Table

Device Configuration Information

Compares configuration details across different devices in the family.

Pin Configuration and Functions

NKD Package 64-Pin WQFN Top View

Illustrates the pinout of the 64-pin WQFN NKD package.

Pin Functions

Details the function of each pin on the device.

Specifications

Absolute Maximum Ratings

Specifies the electrical limits beyond which device damage may occur.

ESD Ratings

Defines the Electrostatic Discharge protection levels for the device.

Recommended Operating Conditions

Lists the conditions under which the device is guaranteed to operate.

Thermal Information

Provides thermal characteristics and resistance values.

Electrical Characteristics

Current Consumption

Details the current consumption for various device configurations.

Input Clock Specifications

Specifies requirements for CLKin and feedback clock inputs.

PLL1 Specifications

Details performance parameters for Phase-Locked Loop 1.

PLL2 Reference Input (OSCin) Specifications

Specifies input requirements for the PLL2 reference clock.

Internal VCO Specifications

Details the performance of the internal Voltage Controlled Oscillators.

Noise Floor

Specifies the noise floor characteristics of the clock outputs.

CLKout Closed Loop Phase Noise Specifications

Defines phase noise for closed-loop operation with VCXO.

CLKout Closed Loop Jitter Specifications

Specifies jitter performance for closed-loop operation with VCXO.

Default Power on Reset Clock Output Frequency

Specifies default clock output frequencies after reset.

Clock Skew and Delay

Details parameters related to clock skew and delay.

LVDS Clock Outputs

Specifies electrical characteristics for LVDS clock outputs.

HSDS Clock Outputs

Details electrical characteristics for HSDS clock outputs.

LVPECL Clock Outputs

Specifies electrical characteristics for LVPECL clock outputs.

LVCMOS Clock Outputs (OSCout)

Details electrical characteristics for LVCMOS OSCout.

DIGITAL OUTPUTS

Specifies characteristics for digital outputs like CLKin_SELX.

DIGITAL INPUTS

Details electrical characteristics for digital inputs.

SPI Interface Timing

Typical Characteristics – Clock Output AC Characteristics

LMK04821 DCLKout2 Phase Noise Plot

Phase noise plot for LMK04821 DCLKout2.

LMK04826B DCLKout2 Phase Noise Plot

Phase noise plot for LMK04826B DCLKout2.

LMK04828B DCLKout2 Phase Noise Plot

Phase noise plot for LMK04828B DCLKout2.

Parameter Measurement Information

Charge Pump Current Specification Definitions

Defines charge pump current measurement parameters.

Differential Voltage Measurement Terminology

Detailed Description

Overview

Provides a general overview of the LMK0482x family features.

Jitter Cleaning

Explains the dual PLL architecture for jitter cleaning.

JEDEC JESD204B Support

Details the device's compliance with JEDEC JESD204B standards.

Three PLL1 Redundant Reference Inputs

Describes the three redundant reference clock inputs for PLL1.

Overview (continued)

Frequency Holdover

Explains the frequency holdover operation.

PLL2 Integrated Loop Filter Poles

Describes the integrated loop filter components for PLL2.

Clock Distribution

Details the clock distribution capabilities of the device.

Overview (continued)

Device Clock Delay

Explains the analog and digital delay features for device clocks.

Glitchless Half Step and Glitchless Analog Delay

Describes features for glitchless delay operations.

Programmable Output Formats

Details the programmable output types for clock outputs.

Overview (continued)

0-Delay

Explains the cascaded and nested 0-delay modes.

Status Pins

Describes the function of the device status pins.

Functional Block Diagram

LMK04821 Block Diagram

Illustrates the functional block diagram for the LMK04821.

Functional Block Diagram (continued)

LMK04826 and LMK04828 Block Diagram

Illustrates the functional block diagram for LMK04826 and LMK04828.

Functional Block Diagram (continued)

Device and SYSREF Clock Output Block

Shows the block diagram for device and SYSREF clock outputs.

Functional Block Diagram (continued)

SYNC/SYSREF Clocking Paths

Illustrates the clocking paths for SYNC and SYSREF signals.

Feature Description

SYNC/SYSREF

Describes the SYNC and SYSREF functionality.

JEDEC JESD204B

Details features related to JEDEC JESD204B.

How To Enable SYSREF

Provides instructions on how to enable SYSREF functionality.

Feature Description (continued)

Setup of SYSREF Example

Provides an example setup procedure for SYSREF.

Feature Description (continued)

SYSREF Modes

Describes different operating modes for SYSREF.

SYSREF Pulser

Details the SYSREF Pulser mode operation.

Digital Delay

Fixed Digital Delay

Explains the fixed digital delay functionality.

Dynamic Digital Delay

Single and Multiple Dynamic Digital Delay Example

SYSREF to Device Clock Alignment

Input Clock Switching

Input Clock Switching - Manual Mode

Describes the manual mode for input clock switching.

Input Clock Switching - Pin Select Mode

Explains the pin select mode for input clock switching.

Input Clock Switching - Automatic Mode

Digital Lock Detect

Calculating Digital Lock Detect Frequency Accuracy

Provides method to calculate frequency accuracy for lock detect.

Holdover

Enable Holdover

Details how to enable the holdover mode.

Fixed (Manual) CPout1 Holdover Mode

Describes manual configuration of CPout1 in holdover mode.

Tracked CPout1 Holdover Mode

Explains tracked configuration of CPout1 in holdover mode.

During Holdover

Describes device operation while in holdover mode.

Holdover (continued)

Exiting Holdover

Explains the methods for exiting holdover mode.

Holdover Mode - Automatic Exit of Holdover

Details automatic exit criteria for holdover mode.

Device Functional Modes

DUAL PLL

Describes the typical dual PLL mode of operation.

0-DELAY Dual PLL

Programming

Recommended Programming Sequence

Outlines the recommended sequence for programming device registers.

Register Maps

Register Map for Device Programming

Provides a comprehensive map of device registers for programming.

Device Register Descriptions

System Functions

Describes registers related to system functions like RESET.

ID_PROD Registers

Details registers containing product identification information.

ID_MASKREV Register

Provides the IC version identifier register.

Device Clock and SYSREF Clock Output Controls

CLKoutX_Y_ODL, CLKoutX_Y_IDL, DCLKoutX_DIV

Controls clock output levels and device clock dividers.

DCLKoutX_DDLY_CNTH, DCLKoutX_DDLY_CNTL

Controls digital delay high and low count values.

DCLKoutX_ADLY, DCLKoutX_ADLY_MUX, DCLKout_MUX

DCLKoutX_HS, SDCLKoutY_MUX, SDCLKoutY_DDLY, SDCLKoutY_HS

SDCLKoutY_ADLY_EN, SDCLKoutY_ADLY

Power Down Functions for Clock Outputs

Output Polarity and Format Controls

SYSREF, SYNC, and Device Config

VCO_MUX, OSCout_MUX, OSCout_FMT

Controls VCO source selection and OSCout parameters.

SYSREF Source Selection

SYSREF Divider and Delay Settings

SYSREF Divider Settings

Sets the division values for SYSREF outputs.

SYSREF Digital Delay Settings

Configures the digital delay values for SYSREF.

SYSREF Pulse Count and Feedback Controls

SYSREF Pulse Count

Sets the number of SYSREF pulses.

Feedback Controls

Controls feedback features for PLL2 and PLL1.

Power Down Controls and Delay Enable

Power Down Controls for OSCin/SYSREF

Controls power down for OSCin and SYSREF functions.

Dynamic Digital Delay Enable

Enables dynamic digital delay for clocks and SYSREF.

Dynamic Digital Delay Step Count

SYNC Parameters

SYNC Synchronization Prevention

CLKin Control

CLKin Enable and Type Controls

Controls CLKin enable and IO type settings.

CLKin Selection Mode Controls

Configures CLKin selection mode and output routing.

CLKin_SEL0 Controls

CLKin_SEL1 Controls and SDIO Readback Type

RESET Pin Control

Holdover Register Settings

Holdover Functions Configuration

Configures holdover functions like LOS and DAC tracking.

Manual DAC Value Settings

DAC Tracking Rate and Trip High Settings

Clock Switch Event Controls

Holdover DLD Count Settings

Sets the holdover digital lock detect count.

PLL1 Configuration

CLKin0 Divider Settings

Configures the CLKin0 divider for PLL1.

CLKin1 Divider Settings

Configures the CLKin1 divider for PLL1.

PLL1 Configuration (continued)

CLKin2 Divider Settings

Configures the CLKin2 divider for PLL1.

PLL1 N Divider

Sets the N divider value for PLL1.

PLL1 Phase Detector Controls

PLL1 DLD Counter Settings

PLL1 Delay Settings

PLL1 Lock Detect Pin Configuration

PLL2 Configuration

PLL2 R Divider Settings

Sets the R divider value for PLL2.

Other PLL2 Functions

PLL2 Calibration and N Divider Settings

PLL2 N Calibration

Configures PLL2 N divider for calibration.

Frequency Calibration Disable

Disables frequency calibration and sets PLL2 N divider.

PLL2 Phase Detector Controls

PLL2 DLD Counter Settings

PLL2 Loop Filter Resistor Settings

PLL2 Loop Filter Capacitor Settings

PLL2 Lock Detect Pin Configuration

Miscellaneous Registers

PLL2 Prescaler and Power Down

Controls PLL2 prescaler and power down settings.

VCO1 Divider

Sets the VCO1 divider value.

Optimization Registers

Registers for optimizing VCO1 phase noise performance.

Miscellaneous Registers (continued)

PLL1 Lock Detect Status

Provides readback access to PLL1 lock detect status.

PLL2 Lock Detect Status

Provides readback access to PLL2 lock detect status.

Readback Access Registers

Readback Access to CLKin Selection and LOS Indicators

Provides readback access to CLKin selection and LOS indicators.

DAC Value Readback

Contains the DAC value for user readback.

SPI Lock Control

Applications and Implementation

Application Information

Provides information on Texas Instruments design tools.

Typical Applications

Lists common application scenarios for the device.

Digital Lock Detect Frequency Accuracy

Explains how to set frequency accuracy for digital lock detect.

Driving CLKin AND OSCin Inputs

Driving CLKin PINS with a Differential Source

Recommends circuits for driving CLKin pins with differential sources.

Driving CLKin Pins with a Single-ended Source

Design Example

Design Requirements

Specifies the clock output requirements for the design example.

Detailed Design Procedure

Outlines the steps for the detailed design procedure.

Device Selection

Discusses the process of selecting the appropriate device.

Device Configuration and Simulation

Device Programming

Application Curves

Do's and Don'ts

Pin Connection Recommendations

Provides recommendations for connecting device pins.

Power Supply Recommendations

Current Consumption / Power Dissipation Calculations

Details calculations for current consumption and power dissipation.

Layout

Layout Guidelines

Provides general guidelines for PCB layout.

Thermal Management

Discusses thermal management considerations for the device.

Layout Example

Device and Documentation Support

Device Support

Information on obtaining device support and documentation.

Development Support

Details available development support tools and resources.

Related Links

Lists quick access links for technical documents and resources.

Electrostatic Discharge Caution

Provides a caution regarding electrostatic discharge.

Mechanical, Packaging, and Orderable Information

PACKAGING INFORMATION

Orderable Device Status

Defines the marketing status of orderable devices.

Packaging Details

Provides details on package type, pins, quantity, and finish.

TAPE AND REEL INFORMATION

REEL DIMENSIONS

Specifies the dimensions related to tape and reel packaging.

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Defines pin 1 orientation for tape and reel assignments.

PACKAGE MATERIALS INFORMATION

Packaging Material Dimensions

Provides dimensions for package materials like length, width, height.

PACKAGE OUTLINE

WQFN Package Outline Dimensions

Details the dimensions of the WQFN package.

Package Outline Notes

Contains general notes regarding the package outline drawing.

EXAMPLE BOARD LAYOUT

Land Pattern Example

Illustrates an example land pattern for PCB layout.

Solder Mask Details

Provides details on solder mask openings and definitions.

EXAMPLE STENCIL DESIGN

Solderpaste Example

Shows an example stencil design for solderpaste application.