LMK04821
,
LMK04826
,
LMK04828
SNAS605AR –MARCH 2013–REVISED DECEMBER 2015
www.ti.com
10.2.3 Design Example
This design example below highlights using the available tools to design loop filters and create programming
map for LMK0482x.
10.2.3.1 Design Requirements
Clocks outputs:
• 1x 245.76 MHz clock for JESD204B ADC, LVPECL.
– This clock requires the best performance in this example.
• 2x 983.04 MHz clock for JESD204B DAC, LVPECL.
• 1x 122.88 MHz clock for JESD204B FPGA block, LVDS
• 3x 10.24 MHz SYSREF for ADC (LVPECL), DAC (LVPECL), FPGA (LVDS).
• 2x 122.88 MHz clock for FPGA, LVDS
For best performance, the highest possible phase detector frequency is used at PLL2. As such a 122.88 MHz
VCXO is used.
10.2.3.2 Detailed Design Procedure
Please note this information is current as of the date of the release of this datasheet. Design tools receive
continuous improvements to add features and improve model accuracy. Please refer to software instructions or
training for latest features.
10.2.3.2.1 Device Selection
Enter the required frequencies into the tools. In this design the LMK04826B VCO0 and LMK04828B VCO1 both
meet the design requirements. VCO0 offers lower noise floor while VCO1 offers improved VCO phase noise
which reduces RMS jitter. Depending on application requirements and simulations one solution may be chosen
over the other. In this case we will choose LMK04828B_VCO1 for improved RMS jitter in the 12 kHz to 20 MHz
integration range. Larger integration ranges may benefit from the lower noise floor of VCO0.
10.2.3.2.1.1 Clock Architect
Only one device of a family will be returned as a possible solution. For the above example, LMK04828B_VCO1.
Under advanced tab, filtering of specific parts can be done using regular expressions in the Part Filter box.
"LMK0482x.*" will filter for only LMK0482x devices (without quotes). More detailed filters can be given such as
the entire part name LMK04826B_VCO0 to force an LMK04826B using VCO0 solution if one is available.
10.2.3.2.1.2 Clock Design Tool
In wizard-mode, select Dual Loop PLL to find LMK0482x devices. If a high frequency and clean reference is
available, it is not required to use dual loop; PLL1 can be powered down and input is then provided via the
OSCin port. When simulating single loop solutions, set PLL1 loop filter block to "0 Hz LBW" and use VCXO as
the reference block.
98 Submit Documentation Feedback Copyright © 2013–2015, Texas Instruments Incorporated
Product Folder Links: LMK04821 LMK04826 LMK04828
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