Texas Instruments LMK04828 User Manual

LMK04821 , LMK04826 , LMK04828
SNAS605AR –MARCH 2013–REVISED DECEMBER 2015 www.ti.com
9.7.7.6 PLL1_DLD_CNT[13:8], PLL1_DLD_CNT[7:0]
Table 57. PLL1_DLD_CNT[13:0]
MSB LSB
0x15C[5:0] 0x15D[7:0]
This register contains the value of the PLL1 DLD counter.
Table 58. Registers 0x15C and 0x15D
BIT REGISTERS NAME POR DEFAULT DESCRIPTION
7:6 0x15C NA 0 Reserved
The reference and feedback of PLL1 must be within the window of phase
error as specified by PLL1_WND_SIZE for this many phase detector
cycles before PLL1 digital lock detect is asserted.
PLL1_DLD
5:0 0x15C 32
Field Value Delay Value
_CNT[13:8]
0 (0x00) Reserved
1 (0x01) 1
2 (0x02) 2
3 (0x03) 3
PLL1_DLD
7:0 0x15D 0 ... ...
_CNT[7:0]
16,382 (0x3FFE) 16,382
16,383 (0x3FFF) 16,383
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Texas Instruments LMK04828 Specifications

General

Brand	Texas Instruments
Model	LMK04828
Category	Motherboard
Language	English