LMK04821
,
LMK04826
,
LMK04828
SNAS605AR –MARCH 2013–REVISED DECEMBER 2015
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9.7.6.6 CLKin_OVERRIDE, HOLDOVER_PLL1_DET, HOLDOVER_LOS_DET, HOLDOVER_VTUNE_DET,
HOLDOVER_HITLESS_SWITCH, HOLDOVER_EN
This register has controls for enabling clock in switch events.
Table 47. Register 0x150
POR
BIT NAME DESCRIPTION
DEFAULT
7 NA 0 Reserved
When CLKin_SEL_MODE = 0/1/2 to select a manual clock input, CLKin_OVERRIDE = 1
CLKin will force that clock input. Used with clock distribution mode for best performance.
6 0
_OVERRIDE 0: Normal, no override.
1: Force select of only CLKin0/1/2 as specified by CLKin_SEL_MODE in manual mode.
5 NA 0 Reserved
This enables the HOLDOVER when PLL1 lock detect signal transitions from high to low.
HOLDOVER
4 0 0: PLL1 DLD does not cause a clock switch event
_PLL1_DET
1: PLL1 DLD causes a clock switch event
This enables HOLDOVER when PLL1 LOS signal is detected.
HOLDOVER
3 0 0: Disabled
_LOS_DET
1: Enabled
Enables the DAC Vtune rail detections. When the DAC achieves a specified Vtune, if this
bit is enabled, the current clock input is considered invalid and an input clock switch event
HOLDOVER
2 0 is generated.
_VTUNE_DET
0: Disabled
1: Enabled
HOLDOVER Determines whether a clock switch event will enter holdover use hitless switching.
1 _HITLESS 1 0: Hard Switch
_SWITCH 1: Hitless switching (has an undefined switch time)
Sets whether holdover mode is active or not.
0 HOLDOVER_EN 1 0: Disabled
1: Enabled
9.7.6.7 HOLDOVER_DLD_CNT[13:8], HOLDOVER_DLD_CNT[7:0]
Table 48. HOLDOVER_DLD_CNT[13:0]
MSB LSB
0x151[5:0] 0x152[7:0]
This register has the number of valid clocks of PLL1 PDF before holdover is exited.
Table 49. Registers 0x151 and 0x152
POR
BIT REGISTERS NAME DESCRIPTION
DEFAULT
7:6 0x151 NA 0 Reserved
The number of valid clocks of PLL1 PDF before holdover mode is exited.
Field Value Count Value
HOLDOVER
5:0 0x151 2
_DLD_CNT[13:8]
0 (0x00) 0
1 (0x01) 1
2 (0x02) 2
... ...
HOLDOVER
7:0 0x152 0
_DLD_CNT[7:0]
16382 (0x3FFE) 16382
16383 (0x3FFF) 16383
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