LMK04821
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LMK04826
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LMK04828
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SNAS605AR –MARCH 2013–REVISED DECEMBER 2015
9.7.7 (0x153 - 0x15F) PLL1 Configuration
9.7.7.1 CLKin0_R[13:8], CLKin0_R[7:0]
Table 50. CLKin0_R[13:0]
MSB LSB
0x153[5:0] 0x154[7:0]
These registers contain the value of the CLKin0 divider.
POR
BIT REGISTERS NAME DESCRIPTION
DEFAULT
7:6 0x153 NA 0 Reserved
The value of PLL1 N counter when CLKin0 is selected.
Field Value Divide Value
5:0 0x153 CLKin0_R[13:8] 0
0 (0x00) Reserved
1 (0x01) 1
2 (0x02) 2
... ...
7:0 0x154 CLKin0_R[7:0] 120
16382 (0x3FFE) 16382
16383 (0x3FFF) 16383
9.7.7.2 CLKin1_R[13:8], CLKin1_R[7:0]
Table 51. CLKin1_R[13:0]
MSB LSB
0x155[5:0] 0x156[7:0]
These registers contain the value of the CLKin1 R divider.
Table 52. Registers 0x155 and 0x156
POR
BIT REGISTERS NAME DESCRIPTION
DEFAULT
7:6 0x155 NA 0 Reserved
The value of PLL1 N counter when CLKin1 is selected.
Field Value Divide Value
5:0 0x155 CLKin1_R[13:8] 0
0 (0x00) Reserved
1 (0x01) 1
2 (0x02) 2
... ...
7:0 0x156 CLKin1_R[7:0] 150
16382 (0x3FFE) 16382
16383 (0x3FFF) 16383
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