Texas Instruments LMK04828 User Manual

LMK04821 , LMK04826 , LMK04828
SNAS605AR –MARCH 2013–REVISED DECEMBER 2015 www.ti.com
9.3.4 SYSREF to Device Clock Alignment
To ensure proper JESD204B operation, the timing relationship between the SYSREF and the Device clock must
be adjusted for optimum setup and hold time. The ts
JESD204B
defines the time between SYSREF and Device
Clock for a specific condition of SYSREF divider and Device Clock digital delay. From this point, the
SYSREF_DDLY. SDCLKoutY_DDLY, DCLKoutX_DDLY_CNTH, DCLKoutDDLY_CNTL, and DCLKoutX_MUX,
SDCKLoutX_ADLY, and so forth. can be adjusted to provide the required setup and hold time between SYSREF
and Device Clock.
It is possible to digitally adjust the SYSREF up to 20 VCO cycles before the SYSREF. So for example with a
2949.12 MHz VCO frequency, ts
JESD204B
+ 20 × (1/VCO Frequency) = –80 ps + 20 × (1/2949.12 MHz) = 6.7 ns.
9.3.5 Input Clock Switching
Manual, pin select, and automatic are three different kinds clock input switching modes can be set with the
CLKin_SEL_MODE register.
Below is information about how the active input clock is selected and what causes a switching event in the
various clock input selection modes.
9.3.5.1 Input Clock Switching - Manual Mode
When CLKin_SEL_MODE is 0, 1, or 2 then CLKin0, CLKin1, or CLKin2 respectively is always selected as the
active input clock. Manual mode will also override the EN_CLKinX bits such that the CLKinX buffer will operate
even if CLKinX is disabled with EN_CLKinX = 0.
If holdover is entered in this mode, then the device will re-lock to the selected CLKin upon holdover exit.
9.3.5.2 Input Clock Switching - Pin Select Mode
When CLKin_SEL_MODE is 3, the pins CLKin_SEL0 and CLKin_SEL1 select which clock input is active.
Configuring Pin Select Mode
The CLKin_SEL0_TYPE must be programmed to an input value for the CLKin_SEL0 pin to function as an input
for pin select mode.
The CLKin_SEL1_TYPE must be programmed to an input value for the CLKin_SEL1 pin to function as an input
for pin select mode.
If the CLKin_SELX_TYPE is set as output, the pin input value is considered "Low."
The polarity of CLKin_SEL0 and CLKin_SEL1 input pins can be inverted with the CLKin_SEL_INV bit.
Table 4 defines which input clock is active depending on CLKin_SEL0 and CLKin_SEL1 state.
Table 4. Active Clock Input - Pin Select Mode, CLKin_SEL_INV = 0
PIN CLKin_SEL1 PIN CLKin_SEL0 ACTIVE CLOCK
Low Low CLKin0
Low High CLKin1
High Low CLKin2
High High Holdover
The pin select mode will override the EN_CLKinX bits such that the CLKinX buffer will operate even if CLKinX is
disabled with EN_CLKinX = 0. To switch as fast as possible, keep the clock input buffers enabled (EN_CLKinX =
1) that could be switched to.
42 Submit Documentation Feedback Copyright © 2013–2015, Texas Instruments Incorporated
Product Folder Links: LMK04821 LMK04826 LMK04828

Texas Instruments LMK04828 Specifications

General

Brand	Texas Instruments
Model	LMK04828
Category	Motherboard
Language	English