Texas Instruments LMK04828 User Manual

LMK04821 , LMK04826 , LMK04828
www.ti.com SNAS605AR –MARCH 2013–REVISED DECEMBER 2015
9.7.2.6 DCLKoutX_DDLY_PD, DCLKoutX_HSg_PD, DCLKout_ADLYg_PD, DCLKout_ADLY_PD,
DCLKoutX_Y_PD, SDCLKoutY_DIS_MODE, SDCLKoutY_PD
This register controls the power down functions for the digital delay, glitchless half step, glitchless analog delay,
analog delay, outputs, and SYSREF disable modes.
Table 21. Registers 0x106, 0x10E, 0x116, 0x11E, 0x126, 0x12E, 0x136
BIT NAME POR DEFAULT DESCRIPTION
Powerdown the device clock digital delay circuitry.
DCLKoutX
7 0 0: Enabled
_DDLY_PD
1: Powerdown
Powerdown the device clock glitchless half step feature.
DCLKoutX
6 1 0: Enabled
_HSg_PD
1: Powerdown
Powerdown the device clock glitchless analog delay feature.
DCLKoutX
5 1 0: Enabled, analog delay step size of one code is glitchless between values 1 to 23.
_ADLYg_PD
1: Powerdown
Powerdown the device clock analog delay feature.
DCLKoutX
4 1 0: Enabled
_ADLY_PD
1: Powerdown
X_Y = 0_1 → 1
X_Y = 2_3 → 1
X_Y = 4_5 → 0 Powerdown the clock group defined by X and Y.
3 CLKoutX_Y_PD X_Y = 6_7 → 0 0: Enabled
X_Y = 8_9 → 0 1: Powerdown
X_Y = 10_11 → 0
X_Y = 12_13 → 1
Configures the output state of the SYSREF
Field Value Disable Mode
0 (0x00) Active in normal operation
1 (0x01) If SYSREF_GBL_PD = 1, the output is a
SDCLKoutY
2:1 0
logic low, otherwise it is active.
_DIS_MODE
2 (0x02) If SYSREF_GBL_PD = 1, the output is a
nominal Vcm voltage
(1)
, otherwise it is
active.
3 (0x03) Output is a nominal Vcm voltage
(1)
0 SDCLKoutY_PD 1 Powerdown SDCLKoutY and set to the state defined by SDCLKoutY_DIS_MODE
(1) If LVPECL mode is used with emitter resistors to ground, the output Vcm will be ~0 V, each pin will be ~0 V.
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Texas Instruments LMK04828 Specifications

General

Brand	Texas Instruments
Model	LMK04828
Category	Motherboard
Language	English