Texas Instruments LMK04828 User Manual

LMK04821 , LMK04826 , LMK04828
SNAS605AR –MARCH 2013–REVISED DECEMBER 2015 www.ti.com
9.3.7 Holdover
Holdover mode causes PLL2 to stay locked on frequency with minimal frequency drift when an input clock
reference to PLL1 becomes invalid. While in holdover mode, the PLL1 charge pump is TRI-STATED and a fixed
tuning voltage is set on CPout1 to operate PLL1 in open loop.
9.3.7.1 Enable Holdover
Program HOLDOVER_EN = 1 to enable holdover mode.
Holdover mode can be configured to set the CPout1 voltage upon holdover entry to a fixed user defined voltage
or a tracked voltage.
9.3.7.1.1 Fixed (Manual) CPout1 Holdover Mode
By programming MAN_DAC_EN = 1, then the MAN_DAC value will be set on the CPout1 pin during holdover.
The user can optionally enable CPout1 voltage tracking (TRACK_EN = 1), read back the tracked DAC value,
then re-program MAN_DAC value to a user desired value based on information from previous DAC read backs.
This allows the most user control over the holdover CPout1 voltage, but also requires more user intervention.
9.3.7.1.2 Tracked CPout1 Holdover Mode
By programming MAN_DAC_EN = 0 and TRACK_EN = 1, the tracked voltage of CPout1 will be set on the
CPout1 pin during holdover. When the DAC has acquired the current CPout1 voltage, the DAC_Locked signal is
set which may be observed on Status_LD1 or Status_LD2 pins by programming PLL1_LD_MUX or
PLL2_LD_MUX respectively.
Updates to the DAC value for the Tracked CPout1 sub-mode occurs at the rate of the PLL1 phase detector
frequency divided by (DAC_CLK_MULT * DAC_CLK_CNTR).
The DAC update rate should be programmed for ≤ 100 kHz to ensure DAC holdover accuracy.
The ability to program slow DAC update rates, for example one DAC update per 4.08 seconds when using 1024
kHz PLL1 phase detector frequency with DAC_CLK_MULT = 16,384 and DAC_CLK_CNTR = 255, allows the
device to look-back and set CPout1 at at previous "good" CPout1 tuning voltage values before the event which
caused holdover to occurre.
The current voltage of DAC value can be read back using RB_DAC_VALUE, see RB_DAC_VALUE .
9.3.7.2 During Holdover
PLL1 is run in open loop mode.
• PLL1 charge pump is set to TRI-STATE.
• PLL1 DLD will be un-asserted.
• The HOLDOVER status is asserted
• During holdover If PLL2 was locked prior to entry of holdover mode, PLL2 DLD will continue to be asserted.
• CPout1 voltage will be set to:
– a voltage set in the MAN_DAC register (MAN_DAC_EN = 1).
– a voltage determined to be the last valid CPout1 voltage (MAN_DAC_EN = 0).
• PLL1 will attempt to lock with the active clock input.
The HOLDOVER status signal can be monitored on the Status_LD1 or Status_LD2 pin by programming the
PLL1_DLD_MUX or PLL2_DLD_MUX register to "Holdover Status."
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Texas Instruments LMK04828 Specifications

General

Brand	Texas Instruments
Model	LMK04828
Category	Motherboard
Language	English