CPout1
VCO0
VCO1
Partially
Integrated
Loop Filter
2X
Mux
R Delay
N Delay
OSCin
OSCin*
DCLKout0
DCLKout0*
SDCLKout1
SDCLKout1*
DCLKout2
DCLKout2*
FB
Mux
2X
Control
Registers
Status_LD2
Device
Control
DCLKout4
DCLKout4*
SDCLKout5
SDCLKout5*
Holdover
CLKin0
CLKin0*
CLKout6
CLKout8
SYSREF Div
CPout2
CLKin0 R
Divider
(1 to 16,383)
N1 Divider
(1 to 16,383)
R2 Divider
(1 to 4,095)
Phase
Detector
PLL1
Phase
Detector
PLL2
N2 Divider
(1 to 262,143)
Clock Distribution Path
N2 Prescaler
(2 to 8)
OSCout/
CLKin2
OSCout*/
CLKin2*
CLKin1/Fin/
FBCLKin
CLKin1*/Fin*/
FBCLKin*
PLL1
N MUX
VCO
MUX
PLL2
N
MUX
DCLKout6
DCLKout6*
SDCLKout3
SDCLKout3*
SDCLKout7
SDCLKout7*
DCLKout8
DCLKout8*
SDCLKout9
SDCLKout9*
DCLKout10*
DCLKout10
SDCLKout11*
SDCLKout11
DCLKout12*
DCLKout12
SDCLKout13*
SDCLKout13
SYNC
System Reference Control
Divider
(8 to 8191)
Status_LD1
RESET/GPO
CLKin_SEL0
CLKin_SEL1
Fin
SCLK
SDIO
CS*
SPI
Div (1-32)
Dig. Delay
A. Delay
A. Delay
Dig. Delay
Div (1-32)
Dig. Delay
A. Delay
A. Delay
Dig. Delay
Div (1-32)
Dig. Delay
A. Delay
A. Delay
Dig. Delay
Div (1-32) Dig. Delay
A. Delay
A. Delay
Dig. Delay
Div (1-32) Dig. Delay
A. Delay
A. Delay
Dig. Delay
Div (1-32) Dig. Delay
A. Delay
A. Delay
Dig. Delay
Div (1-32) Dig. Delay
A. Delay
A. Delay
Dig. Delay
CLKin
MUX
Fin
CLKin2 R
Divider
(1 to 16,383)
SYNC
SPI
Selectable
CLKin1
OUT
MUX
CLKin1 R
Divider
(1 to 16,383)
CLKin0
OUT
MUX
SYNC and SYSREF
SYNC and SYSREF
Pulser
FB Mux
VCO1_DIV
(2 to 8)
LMK04821
,
LMK04826
,
LMK04828
SNAS605AR –MARCH 2013–REVISED DECEMBER 2015
www.ti.com
9.2 Functional Block Diagram
Figure 10 and Figure 11 illustrate the complete LMK0482x family block diagram.
Figure 10. Detailed LMK04821 Block Diagram
32 Submit Documentation Feedback Copyright © 2013–2015, Texas Instruments Incorporated
Product Folder Links: LMK04821 LMK04826 LMK04828
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