Texas Instruments LMK04828 User Manual

LMK04821 , LMK04826 , LMK04828
SNAS605AR –MARCH 2013–REVISED DECEMBER 2015 www.ti.com
9.7.9.4 OPT_REG_2
This register must be written with the following value depending on which LMK0482x family part is used to
optimize VCO1 phase noise performance over temperature. This register must be written before writing register
0x168 when using VCO1.
Table 77. Register 0x17D
BIT NAME DESCRIPTION
51: LMK04821
7:0 OPT_REG_2 119: LMK04826
51: LMK04828
9.7.9.5 RB_PLL1_LD_LOST, RB_PLL1_LD, CLR_PLL1_LD_LOST
Table 78. Register 0x182
BIT NAME DESCRIPTION
7:3 N/A Reserved
2 RB_PLL1_LD_LOST This is set when PLL1 DLD edge falls. Does not set if cleared while PLL1 DLD is low.
Read back 0: PLL1 DLD is low.
1 RB_PLL1_LD
Read back 1: PLL1 DLD is high.
To reset RB_PLL1_LD_LOST, write CLR_PLL1_LD_LOST with 1 and then 0.
0: RB_PLL1_LD_LOST will be set on next falling PLL1 DLD edge.
0 CLR_PLL1_LD_LOST
1: RB_PLL1_LD_LOST is held clear (0). User must clear this bit to allow RB_PLL1_LD_LOST to
become set again.
9.7.9.6 RB_PLL2_LD_LOST, RB_PLL2_LD, CLR_PLL2_LD_LOST
Table 79. Register 0x0x183
BIT NAME DESCRIPTION
7:3 N/A Reserved
2 RB_PLL2_LD_LOST This is set when PLL2 DLD edge falls. Does not set if cleared while PLL2 DLD is low.
PLL1_LD_MUX or PLL2_LD_MUX must select setting 2 (PLL2 DLD) for valid reading of this bit.
1 RB_PLL2_LD Read back 0: PLL2 DLD is low.
Read back 1: PLL2 DLD is high.
To reset RB_PLL2_LD_LOST, write CLR_PLL2_LD_LOST with 1 and then 0.
0: RB_PLL2_LD_LOST will be set on next falling PLL2 DLD edge.
0 CLR_PLL2_LD_LOST
1: RB_PLL2_LD_LOST is held clear (0). User must clear this bit to allow RB_PLL2_LD_LOST to
become set again.
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Texas Instruments LMK04828 Specifications

General

Brand	Texas Instruments
Model	LMK04828
Category	Motherboard
Language	English