Texas Instruments LMK04828 User Manual

LMK04821 , LMK04826 , LMK04828
www.ti.com SNAS605AR –MARCH 2013–REVISED DECEMBER 2015
Electrical Characteristics (continued)
(3.15 V < V
CC
< 3.45 V, –40 °C < T
A
< 85 °C and T
PCB
≤ 105 °C. Typical values at V
CC
= 3.3 V, T
A
= 25 °C, at the
Recommended Operating Conditions and are not assured.)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Single Ended AC coupled
V
FBCLKin/Fin
0.25 2.0 Vpp
Clock Input Voltage CLKinX_TYPE = 0 (Bipolar)
AC coupled; 20% to 80%;
SLEW
FBCLKin/Fin
Slew Rate on CLKin
(2)
0.15 0.5 V/ns
(CLKinX_TYPE = 0)
PLL1 SPECIFICATIONS
f
PD1
PLL1 Phase Detector Frequency 40 MHz
V
CPout1
= V
CC
/2, PLL1_CP_GAIN = 0 50
V
CPout1
= V
CC
/2, PLL1_CP_GAIN = 1 150
V
CPout1
= V
CC
/2, PLL1_CP_GAIN = 2 250
PLL1 Charge
I
CPout1
SOURCE µA
Pump Source Current
(5)
… …
V
CPout1
= V
CC
/2, PLL1_CP_GAIN = 14 1450
V
CPout1
= V
CC
/2, PLL1_CP_GAIN = 15 1550
V
CPout1
=V
CC
/2, PLL1_CP_GAIN = 0 –50
V
CPout1
=V
CC
/2, PLL1_CP_GAIN = 1 –150
V
CPout1
=V
CC
/2, PLL1_CP_GAIN = 2 –250
PLL1 Charge
I
CPout1
SINK µA
Pump Sink Current
(5)
… …
V
CPout1
=V
CC
/2, PLL1_CP_GAIN = 14 –1450
V
CPout1
=V
CC
/2, PLL1_CP_GAIN = 15 –1550
Charge Pump
I
CPout1
%MIS V
CPout1
= V
CC
/2, T = 25 °C 1% 10%
Sink / Source Mismatch
Magnitude of Charge Pump Current 0.5 V < V
CPout1
< V
CC
- 0.5 V
I
CPout1
V
TUNE
4%
Variation vs. Charge Pump Voltage T
A
= 25 °C
Charge Pump Current vs.
I
CPout1
%TEMP 4%
Temperature Variation
Charge Pump TRI-STATE Leakage
I
CPout1
TRI 0.5 V < V
CPout
< V
CC
- 0.5 V 5 nA
Current
PLL 1/f Noise at 10 kHz offset. PLL1_CP_GAIN = 350 µA –117
PN10kHz Normalized to 1 GHz Output dBc/Hz
PLL1_CP_GAIN = 1550 µA –118
Frequency
PLL1_CP_GAIN = 350 µA –221.5
PN1Hz Normalized Phase Noise Contribution dBc/Hz
PLL1_CP_GAIN = 1550 µA –223
PLL2 REFERENCE INPUT (OSCin) SPECIFICATIONS
f
OSCin
PLL2 Reference Input
(6)
500 MHz
PLL2 Reference Clock minimum slew
SLEW
OSCin
20% to 80% 0.15 0.5 V/ns
rate on OSCin
(2)
AC coupled; Single-ended
V
OSCin
Input Voltage for OSCin or OSCin* 0.2 2.4 Vpp
(Unused pin AC coupled to GND)
V
ID
OSCin 0.2 1.55 |V|
Differential voltage swing
AC coupled
Figure 8
V
SS
OSCin 0.4 3.1 Vpp
DC offset voltage between
|V
OSCin-offset
| Each pin AC coupled 20 |mV|
OSCin/OSCin* (OSCinX* - OSCinX)
EN_PLL2_REF_2X = 1
(8)
;
f
doubler_max
Doubler input frequency
(7)
155 MHz
OSCin Duty Cycle 40% to 60%
(5) This parameter is programmable
(6) F
OSCin
maximum frequency assured by characterization. Production tested at 122.88 MHz.
(7) Assured by characterization. ATE tested at 122.88 MHz.
(8) The EN_PLL2_REF_2X bit enables/disables a frequency doubler mode for the PLL2 OSCin path.
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Texas Instruments LMK04828 Specifications

General

Brand	Texas Instruments
Model	LMK04828
Category	Motherboard
Language	English