GPIO
ROM Location:
ROM_APITABLE is an array of pointers located at 0x0100.0010.
ROM_GPIOTABLE is an array of pointers located at ROM_APITABLE[4].
ROM_GPIOPinTypeQEI is a function pointer located at ROM_GPIOTABLE[18].
Parameters:
ui32Port is the base address of the GPIO port.
ui8Pins is the bit-packed representation of the pin(s).
Description:
The QEI pins must be properly configured for the QEI peripheral to function correctly. This
function provides a typical configuration for those pin(s); other configurations may work as well
depending upon the board setup (for example, not using the on-chip pull-ups).
The pin(s) are specified using a bit-packed byte, where each bit that is set identifies the pin to
be accessed, and where bit 0 of the byte represents GPIO port pin 0, bit 1 represents GPIO
port pin 1, and so on.
Note:
This cannot be used to turn any pin into a QEI pin; it only configures a QEI pin for proper
operation.
Returns:
None.
10.2.1.23 ROM_GPIOPinTypeSSI
Configures pin(s) for use by the SSI peripheral.
Prototype:
void
ROM_GPIOPinTypeSSI(uint32_t ui32Port,
uint8_t ui8Pins)
ROM Location:
ROM_APITABLE is an array of pointers located at 0x0100.0010.
ROM_GPIOTABLE is an array of pointers located at ROM_APITABLE[4].
ROM_GPIOPinTypeSSI is a function pointer located at ROM_GPIOTABLE[19].
Parameters:
ui32Port is the base address of the GPIO port.
ui8Pins is the bit-packed representation of the pin(s).
Description:
The SSI pins must be properly configured for the SSI peripheral to function correctly. This
function provides a typical configuration for those pin(s); other configurations may work as well
depending upon the board setup (for example, using the on-chip pull-ups).
The pin(s) are specified using a bit-packed byte, where each bit that is set identifies the pin to
be accessed, and where bit 0 of the byte represents GPIO port pin 0, bit 1 represents GPIO
port pin 1, and so on.
102 April 8, 2013
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