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Texas Instruments TMS320C6455 User Guide
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TMS320C6455/C6454
DSP
DDR2
Memory
Controller
User
'
s
Guide
Literature
Number:
SPRU970G
December
2005
–
Revised
June
2011
2
Table of Contents
Default Chapter
3
Table of Contents
3
Preface
7
Introduction
9
Purpose of the Peripheral
9
Features
9
Functional Block Diagram
9
Industry Standard(S) Compliance Statement
10
Device Block Diagram
10
Peripheral Architecture
11
Clock Control
11
Memory Map
11
Signal Descriptions
11
DDR2 Memory Controller Signals
12
DDR2 Memory Controller Signal Descriptions
12
Protocol Description(S)
13
DDR2 SDRAM Commands
13
Truth Table for DDR2 SDRAM Commands
13
DDR2 MRS and EMRS Command
14
Refresh Command
15
ACTV Command
16
DCAB Command
17
DEAC Command
18
DDR2 READ Command
19
Memory Width, Byte Alignment, and Endianness
20
DDR2 WRT Command
20
Addressable Memory Ranges
20
Address Mapping
21
Byte Alignment
21
Bank Configuration Register Fields for Address Mapping
21
Logical Address-To-DDR2 SDRAM Address Map for 32-Bit SDRAM
22
Logical Address-To-DDR2 SDRAM Address Map for 16-Bit SDRAM
22
Logical Address-To-DDR2 SDRAM Address Map
23
DDR2 Memory Controller Interface
24
DDR2 SDRAM Column, Row, and Bank Access
24
DDR2 Memory Controller FIFO Description
24
DDR2 Memory Controller FIFO Block Diagram
25
Refresh Scheduling
27
Refresh Urgency Levels
27
Self-Refresh Mode
28
2.10 Reset Considerations
28
2.11 DDR2 SDRAM Memory Initialization
28
Device and DDR2 Memory Controller Reset Relationship
28
DDR2 SDRAM Mode Register Configuration
29
DDR2 SDRAM Extended Mode Register 1 Configuration
29
2.12 Interrupt Support
30
2.13 EDMA Event Support
30
2.14 Emulation Considerations
30
Using the DDR2 Memory Controller
31
Connecting the DDR2 Memory Controller to DDR2 SDRAM
31
Connecting to Two 16-Bit DDR2 SDRAM Devices
32
Connecting to a Single 16-Bit DDR2 SDRAM Device
33
Connecting to Two 8-Bit DDR2 SDRAM Devices
34
Configuring DDR2 Memory Controller Registers to Meet DDR2 SDRAM Specifications
35
SDCFG Configuration
35
DDR2 Memory Refresh Specification
36
SDRFC Configuration
36
SDTIM1 Configuration
36
SDTIM2 Configuration
37
DMCCTL Configuration
37
DDR2 Memory Controller Registers
38
Module ID and Revision Register (MIDR)
39
Module ID and Revision Register (MIDR) Field Descriptions
39
DDR2 Memory Controller Status Register (DMCSTAT)
40
DDR2 Memory Controller Status Register (DMCSTAT) Field Descriptions
40
SDRAM Configuration Register (SDCFG)
41
SDRAM Configuration Register (SDCFG) Field Descriptions
41
SDRAM Refresh Control Register (SDRFC)
43
SDRAM Refresh Control Register (SDRFC) Field Descriptions
43
SDRAM Timing 1 Register (SDTIM1)
44
SDRAM Timing 1 Register (SDTIM1) Field Descriptions
44
SDRAM Timing 2 Register (SDTIM2)
46
SDRAM Timing 2 Register (SDTIM2) Field Descriptions
46
Burst Priority Register (BPRIO)
47
Burst Priority Register (BPRIO) Field Descriptions
47
DDR2 Memory Controller Control Register (DMCCTL)
48
DDR2 Memory Controller Control Register (DMCCTL) Field Descriptions
48
Revision History
49
Important Notice
50
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Texas Instruments TMS320C6455 Specifications
General
Brand
Texas Instruments
Model
TMS320C6455
Category
Signal Processors
Language
English
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