Texas Instruments TMS320C6455 User Guide

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4.7 Burst Priority Register (BPRIO)
The Burst Priority Register (BPRIO) helps prevent command starvation within the DDR2 memory
controller. To avoid command starvation, the DDR2 memory controller momentarily raises the priority of
the oldest command in the command FIFO after a set number of transfers have been made. The
PRIO_RAISE bit sets the number of transfers that must be made before the DDR2 memory controller
raises the priority of the oldest command. The BPRIO is shown in Figure 25 and described in Table 24.
For more details on command starvation, see Section 2.7.2.
Figure 25. Burst Priority Register (BPRIO)
31 16
Reserved
R-0
15 8 7 0
Reserved PRIO_RAISE
R-0 R/W-0xFF
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 24. Burst Priority Register (BPRIO) Field Descriptions
Bit Field Value Description
31-8 Reserved 000h Reserved. The reserved bit location is always read as 0. A value written to this field has no effect.
7-0 PRIO_RAISE 0h 1 memory transfer.
1h 2 memory transfers.
...
FEh 255 memory transfers.
FFh EMIF reorders commands based on its arbitration.
47
SPRU970G– December 2005– Revised June 2011 C6455/C6454 DDR2 Memory Controller
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Texas Instruments TMS320C6455 Specifications

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Brand	Texas Instruments
Model	TMS320C6455
Category	Signal Processors
Language	English