Texas Microsystems, Inc. 2003 - Rev A-C Con£Iguration; Schematics £Or Rev D CPU; Schematics £Or Rev A-C CPU

M:lNI'IOR TYPE
SWl-1 DEFAUIll' MJNI'roR TYPE
OPEN ~
CI.DSED COlOR
MEM::>RY CONFIGURATION
SWl-4 SWl-3 SWl-2
BASE / EXPANDED MEM::>RY
ZERO ZERO
256K ZERO
512K ZERO
640K ZERO
OPEN
CI.DSED
CI.DSED
CIDSED
CI.DSED
OPEN
CIDSED
CI.DSED
CI.DSED
OPEN
OPEN
OPEN
CI.DSED
CI.DSED
OPEN
CI.DSED
OPEN
OPEN
512K 512K (above 1Mbyte)
640 384K (above 1Mbyte)
SOFIWARE FEA'IURES
SWl-7 SWl-6 SWl-5 FFA'lURE
CIDSED LOOP ON romRlJP DIAGNOSTICS
CIDSED AUDWS USE OF XI' KEYOOARD
X SWl-7 IS NO!' USED (always OFF)
ROM CONFIGURATION
SWl-8 ROM TYPE
OPEN 27256 (64K'lUI'AL) (STANDARD)
CI.DSED 27512 (128K'lUI'AL)
JUIl'perS E1, E3 a:rrl E4 configure the on-boa:r:d battery, co-processor
clock rate option a:rrl wait state generator options.
FUNCl'ION JUMPER SEl'l'ING
BATl'ERY CONNECl'ED E1-1 to El-2
80287 S'I'ANDARD CIOCK E3-1 to E3-2
E3-6 to E3-4
80287 OPI'IONAL CIOCK E3-1 to E3-3
E3-6 to E3-5
2 WAIT STATES ON 16
BIT IDm:RNAL MEK>RY E4-1 to E4-2
NO WAIT STATE GEN. E4-5 to E4-6 (REK>VE U74)
Preliminary AT Users Manual
27 11/26/86 (11/08/87)