SARA-G3 and SARA-U2 series - System Integration Manual
UBX-13000995 - R26 System description
Page 18 of 217
VSIM = 1.80 V typ. or 2.85 V typ. automatically
generated according to the connected SIM type.
See section 1.8 for functional description.
See section 2.5 for external circuit design-in.
Data input/output for 1.8 V / 3 V SIM
Internal 4.7 k pull-up to VSIM.
See section 1.8 for functional description.
See section 2.5 for external circuit design-in.
3.25 MHz clock output for 1.8 V / 3 V SIM
See section 1.8 for functional description.
See section 2.5 for external circuit design-in.
Reset output for 1.8 V / 3 V SIM
See section 1.8 for functional description.
See section 2.5 for external circuit design-in.
1.8 V input for SIM presence detection function.
Pin configurable also as GPIO on SARA-U2 series.
See section 1.8.2 for functional description.
See section 2.5 for external circuit design-in.
1.8 V output, Circuit 104 (RXD) in ITU-T V.24,
for AT, data, Mux, FOAT on SARA-G3 modules,
for AT, data, Mux, FOAT, FW upgrade via EasyFlash
tool and diagnostics on SARA-U2 modules.
Access by external test-point is recommended.
See section 1.9.1 for functional description.
See section 2.6.1 for external circuit design-in.
1.8 V input, Circuit 103 (TXD) in ITU-T V.24,
for AT, data, Mux, FOAT on SARA-G3 modules,
for AT, data, Mux, FOAT, FW upgrade via EasyFlash
tool and diagnostics on SARA-U2 modules.
Internal active pull-up to V_INT.
Access by external test-point is recommended.
See section 1.9.1 for functional description.
See section 2.6.1 for external circuit design-in.
UART clear to
send output
1.8 V output, Circuit 106 (CTS) in ITU-T V.24.
Access by external test-point is recommended.
See section 1.9.1 for functional description.
See section 2.6.1 for external circuit design-in.
1.8 V input, Circuit 105 (RTS) in ITU-T V.24.
Internal active pull-up to V_INT.
Access by external test-point is recommended.
See section 1.9.1 for functional description.
See section 2.6.1 for external circuit design-in.
UART data set
ready output
1.8 V output, Circuit 107 (DSR) in ITU-T V.24.
See section 1.9.1 for functional description.
See section 2.6.1 for external circuit design-in.
UART ring
indicator output
1.8 V output, Circuit 125 (RI) in ITU-T V.24.
See section 1.9.1 for functional description.
See section 2.6.1 for external circuit design-in.
UART data
terminal ready
input
1.8 V input, Circuit 108/2 (DTR) in ITU-T V.24.
Internal active pull-up to V_INT.
See section 1.9.1 for functional description.
See section 2.6.1 for external circuit design-in.
UART data carrier
detect output
1.8 V input, Circuit 109 (DCD) in ITU-T V.24.
See section 1.9.1 for functional description.
See section 2.6.1 for external circuit design-in.