SARA-G3 and SARA-U2 series - System Integration Manual
UBX-13000995 - R26 Design-in
Page 174 of 217
2.16 Design-in checklist
This section provides a design-in checklist.
2.16.1 Schematic checklist
The following are the most important points for a simple schematic check:
DC supply must provide a nominal voltage at the VCC pin above the minimum operating range limit.
DC supply must be capable of providing 1.9 A current pulses, providing a voltage at VCC pin above the
minimum operating range limit and with a maximum 400 mV voltage drop from the nominal value.
VCC supply should be clean, with very low ripple/noise: provide the suggested bypass capacitors (and
series ferrite bead for a SARA-U201), in particular if the application device integrates an internal
antenna.
VCC voltage must ramp from 2.5 V to 3.2 V within 4 ms to allow a proper switch-on of the module.
Do not leave PWR_ON floating: fix properly the level, e.g. adding a proper pull-up resistor to V_BCKP.
Do not apply loads which might exceed the limit for maximum available current from V_INT supply.
Check that the voltage level of any connected pin does not exceed the relative operating range.
Capacitance and series resistance must be limited on each SIM signal to match the SIM specifications.
Insert the suggested capacitors on each SIM signal and low capacitance ESD protections if accessible.
Check UART signals direction, since the signal names follow the ITU-T V.24 Recommendation [10].
Provide accessible test-points directly connected to the following pins of the SARA-G3 series modules:
TXD_AUX and RXD_AUX pins, GPIO3 and I
2
S pins, V_INT pin, RESET_N and/or PWR_ON pins, for
module FW upgrade by the u-blox EasyFlash tool and/or for diagnostic purposes.
Provide accessible test-points directly connected to the following pins of the SARA-U2 series modules:
VUSB_DET, USB_D+, USB_D- and/or RXD, TXD, CTS, RTS pins, V_INT pin, RESET_N and/or PWR_ON
pins, for module FW upgrade by the u-blox EasyFlash tool and/or for diagnostic purposes.
Add a proper pull-up resistor (e.g. 4.7 k) to V_INT or another proper 1.8 V supply on each DDC (I
2
C)
interface line, if the interface is used.
Capacitance and series resistance must be limited on each high speed line of the USB interface.
Capacitance and series resistance must be limited on each line of the DDC (I
2
C) interface.
Use transistors with at least an integrated resistor in the base pin or otherwise put a 10 k resistor on
the board in series to the GPIO when those are used to drive LEDs.
Connect the pin number 33 (RSVD) to ground.
Insert the suggested passive filtering parts on each used analog audio line.
Check the digital audio interface specifications to connect a proper device.
Capacitance and series resistance must be limited on CODEC_CLK line and each I
2
S interface line.
Provide proper precautions for ESD immunity as required on the application board.
Any external signal connected to any generic digital interface pin must be tri-stated or set low when the
module is in power-down mode and during the module power-on sequence (at least until the activation
of the V_INT output of the module), to avoid latch-up of circuits and let a proper boot of the module.
All unused pins can be left unconnected except the PWR_ON pin (its level must be properly fixed, e.g.
adding a 100 k pull-up to V_BCKP) and the RSVD pin number 33 (it must be connected to GND).
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