VIPA CPU 214 User Manual

Manual VIPA CPU 21x Chapter 11 Integrated OBs SFBs SFCs
HB103E - Rev. 05/45 11-29
Page frame communication - Parameter
The delivered handling blocks allow the deployment of communication
processors in the CPUs from VIPA.
This increases the efficiency markable.
The handling blocks control the complete data transfer between CPU and
the CPs.
Advantages of the handling blocks:
• you loose only few user application memory space
• short runtimes of the blocks
The handling blocks don't need:
• bit memory area
• time areas
• counter areas
All handling blocks described in the following use an identical interface to
the user application with this parameters:
SSNR: Interface number
ANR: Order number
ANZW: Indicator word (double word)
IND: Indirect fixing of the relative start address of
the data source res. destination
QANF/ZANF: Relative start address within the type
PAFE: Parameterization error
BLGR: Block size
A description of these parameters follows on the next pages.
General
Parameter
description
11x 21x 31x 51x
✓ ✓ ✓

VIPA CPU 214 Specifications

General

Type	CPU 214
Number of timers	256
Number of counters	256
Digital Outputs	16
Analog Inputs	4
Analog Outputs	2
Communication Ports	1
Communication	MPI
Interface	RS485
Transmission rate	187.5 kbit/s
Protocol	MPI
S7-compatible commands	Yes
Number of modules	8
Power Supply	24V DC
Current consumption (with load)	500 mA
Protection Class	IP20
Weight	500g
Operating Temperature	0°C to 60°C
Processor	32-bit
Number of flags	256