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General| Brand | VIPA |
|---|---|
| Model | CPU 21 Series |
| Category | Control Unit |
| Language | English |
Important safety guidelines for handling VIPA modules and preventing electrostatic discharge.
Guidance on using the MPI interface and the 'Green Cable' for data transfer between CPUs and PCs.
General description of the VIPA CPU 21x family, including its versions and features.
Requirements and steps for project engineering using Siemens SIMATIC Manager and GSD files.
Explanation of the CPU's operating modes: STOP, START-UP, and RUN, and their characteristics.
Overview of the CPU 21x family, its versions, and key properties like instruction set compatibility and memory.
Details on the CPU 21x, including its instruction set compatibility, MPI interface, and memory.
Description of the CPU 21x-2BT10, highlighting its Ethernet capabilities and additional features.
Details on the CPU 21xDPM, focusing on its integrated Profibus-DP master functionality.
Description of the components of the CPU 21x, including LEDs, function selector, MMC slot, and power supply.
Comprehensive technical data for CPU 21x, including electrical, dimensional, and module-specific specifications.
Step-by-step instructions for physically installing the CPU modules into the System 200V rack.
Explanation of the CPU's start-up sequence after power-on, reset, or data transfer.
Details on how peripheral modules are addressed automatically and how to modify allocations.
Information on using Siemens SIMATIC Manager and GSD files for project engineering and module addressing.
Methods for transferring projects to the CPU via MPI or MMC, including essential steps and considerations.
Description of the three operating modes: STOP, START-UP, and RUN, and their characteristics.
Guidance on updating the CPU firmware using an MMC, including precautions and procedures.
Explanation of communication protocols like TCP/IP, UDP, and RFC1006 used for Ethernet communication.
Details on IP address structure, subnet masks, and initial IP assignment for network configuration.
Guidelines and standards for planning industrial Ethernet networks, including topology and cable selection.
Overview of communication types supported by the CP, including PG/OP and configurable connections.
Steps for configuring the hardware using Siemens SIMATIC Manager, including GSD file integration.
Instructions for configuring communication connections between stations using NetPro, defining partner types and connection parameters.
Explanation of using SEND/RECEIVE blocks (FC5, FC6) for cyclic data transfer between CPU and CP.
Troubleshooting guide for common communication errors using NCM diagnostic tools.
Basic principles of network topologies, twisted pair cabling, hubs, and switches used in Ethernet networks.
Detailed explanation of TCP/IP protocols, IP addressing, and the functions of TCP and UDP.
Information on Ethernet MAC addresses, IP address structure, and broadcast addresses.
Procedure for project engineering including CP configuration with WinNCS, hardware configuration, and PLC programming.
Steps for configuring the CP using VIPA WinNCS, covering initial CP setup and connection configuration.
Details on PLC programming for connection requests using SEND, RECEIVE, and SYNCHRON blocks.
Explanation of the CPU 21x-2BT02 and CP start-up behavior, including synchronization and status changes.
Introduction to Profibus-DP, its principles, and the distinction between masters and slaves.
Steps for project engineering the CPU 21xDPM as a Profibus-DP master using Siemens SIMATIC Manager.
Methods for transferring projects to the CPU via MPI or MMC, including specific steps for configuration.
Description of the DP master's operating modes: STOP→RUN (automatically) and RUN.
Guidance on commissioning the CPU 21xDPM, including system setup, project transfer, and default boot procedures.
Introduction to Profibus-DP, its principles, and the distinction between masters and slaves.
Steps for configuring the CPU 21xDP as a Profibus-DP slave using Siemens SIMATIC Manager and GSD files.
Details on configuring DP slave parameters, including input/output areas and CPU memory release.
Explanation of Profibus-DP diagnostic functions, standard and device-related data structures, and starting diagnostics.
Guidelines for installing Profibus networks, including structure, medium, addressing, and termination.
Steps for commissioning the CPU 21xDP, including installation, master system configuration, and voltage supply.
Introduction to CAN-Bus principles, CANopen as a user profile, and communication objects like PDOs and SDOs.
Steps for project engineering the CANopen master using WinCoCT and Siemens SIMATIC Manager.
Instructions for hardware configuration of the System 200V modules and CPU 21xCAN using Siemens tools.
Description of the operating modes for the CAN master: STOP→RUN (automatically) and RUN.
Details on the CPU 21xCAN process image for input (RPDOs) and output (TPDOs) data.
Structure and content of the CANopen object directory, including communication-specific and standardized device profile areas.
Overview of CPU 21xSER-1 serial interfacing facilities, supported protocols, and SFCs for serial communication.
Explanation of ASCII, STX/ETX, 3964R, USS, and Modbus protocols and their procedures.
Description of the RS232C and RS485 interfaces, including pin assignments and electrical characteristics.
Illustration of data transfer principles using SFCs, FIFO buffers, and protocols like ASCII, STX/ETX, 3964R, USS, Modbus.
Details on parameterizing serial interfaces using SFC 216 (SER_CFG) and data blocks for different protocols.
Explanation of communication via send/receive blocks (SFC 217, SFC 218) and their usage with different protocols.
An example demonstrating Modbus communication between a master and slave CPU 21xSER-1.
Overview of CPU 21x-2BS02 serial interfacing facilities, its two RS232C interfaces, and supported protocols.
Explanation of ASCII, STX/ETX, 3964(R), and RK512 protocols and their procedures.
Detailed description of the RS232C interface, its properties, pin assignments, and supported signals.
Explanation of data communication controlled by handler blocks (SFCs) for CPU-CP interaction.
Steps for initializing serial interfaces using SFC 235 (SYNCHRON) in OB100, including block size configuration.
Details on interface parameter transfer using SFC 230 (SEND) and SFC 234 (RESET), including parameter structures for various protocols.
Overview of integrated Organization Blocks (OBs) and System Function Blocks (SFBs) available in the CPU 21x.
List and description of standard System Function Calls (SFCs) provided by Siemens.
Description of VIPA-specific SFCs, their assignment to CPU families, and inclusion procedure.
Details on SFC 216 SER_CFG for RS232C parameterization, including protocols and parameter blocks.
Explanation of SFC 217 SER_SND for sending data via the RS232C interface, including parameters and error messages.
Details on SFC 218 SER_RCV for receiving data via the RS232C interface, including parameters and error messages.
Information on SFC 220 MMC_CR_F for creating or accessing files on MMC, including restrictions and parameters.
Details on SFC 221 MMC_RD_F for reading data from MMC, including parameters and return values.
Explanation of SFC 222 MMC_WR_F for writing data to MMC, including parameters and return values.
Details on SFC 223 PWM for parameterizing pulse duration modulation for output channels.
Information on SFC 224 HSC for parameterizing high-speed counter functions for input channels.
Details on SFC 225 HF_PWM for parameterizing pulse duration modulation with frequency for output channels.
Explanation of SFC 227 TD_PRM for connecting the TD200 terminal from Siemens to VIPA CPUs.
Details on SFC 228 RW_KACHEL for direct access to the CPU page frame area for read/write operations.
Description of handling blocks for communication processors and their parameters like SSNR, ANR, ANZW, IND.
Explanation of direct and indirect parameter transfer methods for handling blocks using SFC 230.
Structure and meaning of the indicator word ANZW for status and error reports of communication orders.
Table of important indicator word states for SEND, RECEIVE, and READ/WRITE-ACTIVE operations.
Details on the SFC 230 SEND block for initializing a send order to a CP, including parameters and conditions.
Explanation of the SFC 231 RECEIVE block for receiving data from a CP, including parameters and activation conditions.
Details on the SFC 236 SEND_ALL block for transmitting data from CPU to CP using the declared block size.
Explanation of the SFC 237 RECEIVE_ALL block for transmitting data received from CP to CPU.
An alphabetical listing of all available commands for the VIPA CPUs, including their syntax and page references.
A list of abbreviations used in the manual, with their corresponding descriptions for clarity.
Description of the ACCU and Address Register (AR) used for data processing and addressing.
Illustrative examples of immediate and direct addressing modes for accessing operands and memory locations.
Details on fixed-point, floating-point arithmetic, and trigonometric instructions, including operands and status word effects.
Information on block call instructions (CALL, UC) and block end instructions (BE, BEU, BEC).
Description of various jump instructions based on conditions, RLO, BR, and CC bits.
Explanation of instructions for transferring data between ACCU and addressed operands, including register indirect and area crossing.
Details on instructions for converting data types between BCD, integer, real, and double integer formats.
Explanation of instructions used for comparing integer and real numbers in ACCU1 and ACCU2.
Instructions for combining signal states of addressed operands using AND, AN, O, ON, X, XN logic.
Description of instructions for starting, resetting, and controlling timers with various edge triggers and parameters.
Details on instructions for presetting, resetting, incrementing, decrementing, and enabling counters.
Information on VIPA-specific event-IDs found in the CPU diagnostic buffer for troubleshooting.
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