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VIPA CPU 21 Series User Manual

VIPA CPU 21 Series
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Manual VIPA CPU 21x Chapter 11 Integrated OBs SFBs SFCs
HB103E - Rev. 05/45 11-29
Page frame communication - Parameter
The delivered handling blocks allow the deployment of communication
processors in the CPUs from VIPA.
This increases the efficiency markable.
The handling blocks control the complete data transfer between CPU and
the CPs.
Advantages of the handling blocks:
you loose only few user application memory space
short runtimes of the blocks
The handling blocks don't need:
bit memory area
time areas
counter areas
All handling blocks described in the following use an identical interface to
the user application with this parameters:
SSNR: Interface number
ANR: Order number
ANZW: Indicator word (double word)
IND: Indirect fixing of the relative start address of
the data source res. destination
QANF/ZANF: Relative start address within the type
PAFE: Parameterization error
BLGR: Block size
A description of these parameters follows on the next pages.
General
Parameter
description
11x 21x 31x 51x

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VIPA CPU 21 Series Specifications

General IconGeneral
BrandVIPA
ModelCPU 21 Series
CategoryControl Unit
LanguageEnglish

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