VIPA CPU 21 Series User Manual

Chapter 3 Deployment CPU 21x Manual VIPA CPU 21x
3-4 HB103E - Rev. 05/45
Address allocation
To provide specific addressing of the installed peripheral modules, certain
addresses must be allocated in the CPU.
The CPU contains a peripheral area (addresses 0 ... 1023) and a process
image of the inputs and the outputs (for both each address 0 ... 127).
When the CPU is initialized it automatically assigns peripheral addresses to
the digital input/output modules starting from 0.
If there is no hardware projecting, analog modules are allocated to even
addresses starting from address 128.
The signaling states of the lower addresses (0 ... 127) are additionally
saved in a special memory area called the process image.
The process image is divided into two parts:
• process image of the inputs (PII)
• process image of the outputs (PIQ)
Peripheral area
0
.
.
.
127
128
.
.
.
1023
Process image
0
.
.
.
127
0
.
.
.
127
Inputs
PII
Outputs
PIQ
Digital modules
Analog modules
The process image is updated automatically when a cycle has been
completed.
You may access the modules by means of read or write operations on the
peripheral bytes or on the process image.
Note!
Please remember that you may access different
modules by means of read
and write operations on the same address.
The addressing ranges of digital and analog modules are different when
they are addressed automatically.
Digital modules: 0 ... 127
Analog modules: 128 ... 1023
Automatic
addressing
Signaling states in
the process image
Read/write access

VIPA CPU 21 Series Specifications

General

Brand	VIPA
Model	CPU 21 Series
Category	Control Unit
Language	English