Chapter 4 Deployment of the CPU 21x-2BT10 with TCP/IP Manual VIPA CPU 21x
4-32 HB103E - Rev. 05/45
SEND/RECEIVE with PLC program
For the execution of connection commands at the PLC, your CPU requires
an user application. For this, exclusively the VIPA handling blocks
AG_SEND (FC5) and AG_RECV (FC6) are used. By including these blocks
into the cycle block OB1 you may send and receive data cyclic.
The two FCs are part of the VIPA library, that is included in the
consignment as CD (SW830).
Note!
Please regard that you may only use the SEND/RECV-FCs from VIPA in
your user application for the communication with VIPA-CPs. At a change to
VIPA-CPs in an already existing project, the present AG_SEND/ AG_LSEND
res. AG_RECV/AG_LRECV may be replaced by AG_SEND res. AG_RECV
from VIPA without adjustment. Due to the fact that the CP automatically
adjusts itself to the length of the data to transfer, the L and F variants of
SEND res. RECV are not required for VIPA CPs.
For the communication between CPU and CP, the following FCs are
available:
AG_SEND (FC5)
This block transfers the user data from the data area given in SEND to the
CP specified via ID and LADDR. As data area you may set a PA, bit
memory or data block area. When the data area has been transferred
without errors, "order ready without error” is returned.
AG_RECV (FC6)
The block transfers the user data from the CP into a data area defined via
RECV. As data area you may set a PA, bit memory or data block area.
When the data area has been transferred without errors, "order ready
without error” is returned.
The CP processes send and receive commands independently from the
CPU cycle and needs for this transfer time. The interface with the FC
blocks to the user application is here synchronized by means of
acknowledgements/receipts.
For status evaluation the communication blocks return parameters that
may be evaluated directly in the user application.
These status displays are updated at every block call.
Do not use cyclic calls of the communication blocks in OB1. This causes a
permanent communication between CPU and CP. Program instead the
communication blocks within a time OB where the cycle time is higher res.
event controlled.
Overview
Communication
blocks
Status displays
Deployment at high
communication load
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