Manual VIPA System 300V Chapter 3 Profibus DP
HB130E - IM - Rev. 08/26 3-7
A bus cycle saves all the input data from the modules in the PII and all the
output data from the PIQ in the output modules. When the data has been
saved the PII is transferred into the ”send buffer” and the contents of the
”receive buffer” is transferred into PIQ.
During a Profibus cycle the master addresses all its slaves according to the
sequence defined in the data exchange. The data exchange reads and
writes data from/into the memory areas assigned to the Profibus.
The contents of the Profibus input area is entered into the ”receive buffer”
and the data in the ”send buffer” is transferred into the Profibus output
area.
The exchange of data between DP master and DP slave is completed
cyclically and it is independent from the bus cycle.
To ensure that the data transfer is synchronized the bus cycle time should
always be less than or equal to the DP cycle time.
The parameter min_slave_interval = 3ms is located in the GSD-file.
In an average system it is guaranteed that the Profibus data on the bus is
updated after a max. time of 3ms. You can therefore exchange data with
the slave at intervals of 3ms.
Note!
Starting with release version 6, the RUN-LED of a DP-V0 slave extinguishes
as soon as the Bus cycle lasts longer than the DP cycle. This function is de-
activated at the employment of a DP-V1 slave as DP-V0.
Bus cycle
DP cycle
Bus cycle ≤
≤≤
≤
DP cycle
To Next Page
Loading...
