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General| S7 compatible commands | Yes |
|---|---|
| MPI interface | Yes |
| PROFIBUS DP interface | No |
| Ethernet interface | No |
| Integrated I/O | No |
| Power Supply | 24 V DC |
| Mounting | DIN rail |
| Protection Class | IP20 |
| Communication Ports | MPI |
| Weight | 0.3 kg |
| Operating Temperature | 0°C to 60°C |
Document contains proprietary information of VIPA, not to be disclosed or used without agreement.
Describes the SPEED7 CPU-SC 312-5BE13, covering construction, project implementation, and usage.
Details safety precautions for system operation, applications, and documentation personnel.
Highlights sensitivity of MOS components to electrostatic discharge and handling precautions.
Explains CPU's internal program memory, SPEED7 technology, and modes of operation.
Details the CPU's architecture, programming tools, memory, interfaces, and technical data.
Provides conformity, approval, technical specifications, dimensions, and environmental conditions.
Specifies the physical dimensions for mounting the basic enclosure.
Details module installation on a profile rail and backplane bus connector usage.
Provides instructions for wiring power supply, modules, and using CageClamp technology.
Offers guidance on interference-free deployment and electromagnetic compatibility (EMC).
Lists key features including SPEED7 technology, memory, interfaces, and I/O capabilities.
Details the CPU's components: LEDs, slots, switches, and interfaces under the front flap.
Describes power supply, MPI, PtP, and Ethernet PG/OP interfaces with connector details.
Details digital input/output channels and technological functions integrated into the CPU casing.
Explains the CPU's integrated memory structure: load, code, data, and work memory.
Describes the use of MMC cards for applications, firmware, and project storage.
Explains the rechargeable battery's function for safeguarding RAM and internal clock.
Details how to switch CPU between STOP, RUN, and MRES modes.
Describes the status indication LEDs for CPU, Ethernet PG/OP channel, and their meanings.
Provides comprehensive technical specifications for power supply, digital I/O, and analog functions.
Refers to Chapter 3 for detailed information on assembly and cabling procedures.
Explains CPU behavior upon power-on, default boot, and boot with valid/empty configuration.
Covers addressing of peripheral modules, I/O areas, and automatic address allocation.
Details default addresses and assignments for digital inputs/outputs and counters.
Guides on configuring the CPU using Siemens hardware configurator and SIMATIC Manager.
Explains how to place and parameterize System 300 modules in hardware configuration.
Details setting up the Ethernet PG/OP channel, IP address assignment, and initialization.
Covers setting CPU parameters like name, interface, startup behavior, and clock memory.
Outlines methods for transferring projects to the CPU via MPI, Ethernet, or memory card.
Explains how to access the CPU's web page via Ethernet PG/OP channel for firmware info.
Describes the CPU's operating modes: STOP, START-UP, RUN, and HALT.
Details security mechanisms like Watchdog and cycle time surveillance for error handling.
Explains how to perform an overall reset using the operating mode switch or SIMATIC Manager.
Guides on updating CPU firmware via MMC, including precautions and version checking.
Details the procedure to reset the CPU to its delivery state, including IP and MPI address resets.
Describes automatic project loading and command file execution from storage media.
Explains how to extend work memory using a MCC memory extension card.
Details VIPA's extended protection for secure block storage and access control.
Describes auto-execution of command files from MMC for tasks like project loading and network setup.
Lists VIPA-specific event IDs for troubleshooting and diagnostic buffer monitoring.
Explains using Debug > Monitor and PLC > Monitor/Modify Variables for troubleshooting.
Introduces digital in-/output and technological functions integrated into the 2tier casing.
Details the CPU's digital I/O channels and technological functions with pin assignments.
Specifies default addresses and assignments for input and output ranges.
Covers digital inputs, outputs, and technological functions with parameterization options.
Explains default addresses used for input/output data without hardware configuration.
Details parameters for digital part configuration, including hardware interrupts and input delay.
Introduces counter functions, modes, and parameterization via the Count submodule.
Explains counting pulses during integration time and outputting frequency values.
Describes PWM generation via time parameters, pulse/break ratio, and output channels.
Details triggers for hardware interrupts, process interrupts, and diagnostic interrupts.
Introduces PtP communication via RS485 interface and supported protocols.
Illustrates data transfer using FC/SFCs, FIFO buffers, and protocol embedding.
Details RS485 interface properties: logical states, bus connection, and data communication limits.
Covers runtime parameterization using FC/SFC 216 (SER_CFG) for various protocols.
Explains communication via send/receive blocks FC/SFC 217 (SER_SND) and 218 (SER_RCV).
Describes supported protocols: ASCII, STX/ETX, 3964R, USS, and Modbus with message structures.
Details Modbus function codes for master access to slave devices, including range definitions.
Introduces WinPLC7 as VIPA's programming and simulation software for PLCs.
Covers WinPLC7 installation, system requirements, and activation of the 'Profi' version.
Guides through creating a project, configuring hardware, and programming FC 1 for comparison.
Details testing PLC programs using the WinPLC7 simulator, including process image viewing.
Explains transferring the PLC program to the CPU via Ethernet and executing it.
Introduces TIA Portal, its work environment, and starting/exiting the application.
Guides on configuring the VIPA CPU as Siemens CPU 312C in TIA Portal.
Details placing and configuring System 300 modules via drag & drop in TIA Portal.
Explains configuring the Ethernet PG/OP channel, IP address assignment, and initialization.
Guides on importing the VIPA library for using VIPA-specific blocks in TIA Portal projects.
Outlines methods for transferring projects to the CPU via MPI, Ethernet, or memory card.
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