EasyManua.ls Logo

VIPA CPU 312SC - SFB 49 - PULSE - Pulse Width Modulation

VIPA CPU 312SC
185 pages
To Next Page IconTo Next Page
To Next Page IconTo Next Page
To Previous Page IconTo Previous Page
To Previous Page IconTo Previous Page
Loading...
Period (Period duration)
n With the period duration the length of the output sequence (pulse
duration/pulse pause) is defined
n Range of values: 1 ... 65535ms respectively 0.4 ... 6553.5ms
n Default value: 20000
Minimum pulse duration
n You can set a minimum pulse time for the attenuation of short
output pulses/pauses. This suppresses all pulses or pauses
shorter than the minimum pulse time. Thus you may filter very
small pulses (spikes), which are not noted from the periphery any-
more.
n Range of values:
0 ... Period duration/2 * 1ms respectively
2 ... Period duration/2 * 0.1ms
n Default: 2
6.7.3 SFB 49 - PULSE - Pulse width modulation
The SFB 49 is a specially developed block for the CPU 31xSC for
pulse width modulation
n The SFB PULSE should cyclically be called (e.g. OB 1) for con-
trolling the frequency measurement.
n The SFB is to be called with the corresponding instance DB. Here
the parameters of the SFB are stored.
n Among others the SFB 49 contains a request interface. Hereby
you get read and write access to the registers of the pulse width
modulation.
n So that a new job may be executed, the previous job must have
be finished with JOB_DONE = TRUE.
n Per channel you may call the SFB in each case with the same
instance DB, since the data necessary for the internal operational
are stored here. Writing accesses to outputs of the instance DB is
not permissible.
n With the SFB PULSE (SFB 49) you have following functional
options:
Start/Stop the pulse width modulation via software gate
SW_GATE
Enabling/controlling of the PWM output
Read status bits
Request to read/write internal registers of the pulse width mod-
ulation
Name Declara-
tion
Data type Address
(Inst.-DB)
Default
value
Comment
LADDR INPUT WORD 0.0 300h This parameter is not evalu-
ated. Always the internal I/O
periphery is addressed.
CHANNEL INPUT INT 2.0 0 Channel number
SW_EN INPUT BOOL 4.0 FALSE Enables the Software gate
OUTP_VAL INPUT INT 6.0 0 Output value
Description
Parameters
VIPA System 300S Deployment I/O periphery
Pulse width modulation - PWM > SFB 49 - PULSE - Pulse width modulation
HB140 | CPU-SC | 312-5BE13 | GB | 15-50 129

Table of Contents

Related product manuals