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VIPA CPU 312SC - Function security

VIPA CPU 312SC
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n All times are frozen.
n The real-time clock runs is just running.
n The outputs were disabled (BASP is activated).
n Configured CP connections remain exist.
The usage of breakpoints is always possible. Switching to
the operating mode test operation is not necessary.
With more than 2 breakpoints, a single step execution is
not possible.
5.11.2 Function security
The CPUs include security mechanisms like a Watchdog (100ms)
and a parametrizable cycle time surveillance (parametrizable min.
1ms) that stop res. execute a RESET at the CPU in case of an error
and set it into a defined STOP state. The VIPA CPUs are developed
function secure and have the following system properties:
Event concerns Effect
RUN ® STOP general BASP (Befehls-Ausgabe-Sperre, i.e. com-
mand output lock) is set.
central digital outputs The outputs are disabled.
central analog outputs The outputs are disabled.
n Voltage outputs issue 0V
n Current outputs 0...20mA issue 0mA
n Current outputs 4...20mA issue 4mA
If configured also substitute values may be
issued.
decentral outputs Same behavior as the central digital/analog
outputs.
decentral inputs The inputs are cyclically be read by the
decentralized station and the recent values
are put at disposal.
STOP ® RUN res.
PowerON
general First the PII is deleted, then OB 100 is
called. After the execution of the OB, the
BASP is reset and the cycle starts with:
Delete PIO ® Read PII ® OB 1.
decentral inputs The inputs are once be read by the decen-
tralized station and the recent values are
put at disposal.
RUN general The program execution happens cyclically
and can therefore be foreseen: Read PII ®
OB 1 ® Write PIO.
PII: Process image inputs, PIO: Process image outputs
VIPA System 300S Deployment CPU 312-5BE13
Operating modes > Function security
HB140 | CPU-SC | 312-5BE13 | GB | 15-50 61

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