VIPA System 300V - Page 67

Manual VIPA System 300V Chapter 3 Profibus DP
HB130E - IM - Rev. 08/26 3-41
The CPU should have a short cycle time to ensure that the data from slave
no. 5 (on the right) is always up to date. This type of structure is only
suitable when the data from slaves on the slow trunk (on the left) is not
critical. You should therefore not connect modules that are able to issue
interrupts.
IM 353
1
In-/Output periphery
IM 353
2
In-/Output periphery
IM 353
4
In-/Output periphery
IM 353
5
In-/Output periphery
IM 353
3
In-/Output periphery
CPU
CPU 31xDPM
1,2,3,4,5
s
low due to many connections
i.e. transferred data are no
t
up to date
CPU with
short cycle time
Gets fast update
With short CPU cycle time, the data of the
IM connection No. 5 is always up to date
Examples for
Profibus network
One CPU and
multiple master
connections