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Wise TSW200E1 - E1;G.704 Module

Wise TSW200E1
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TSW200E1
Rec. G.822. There are histograms for errored bits, errored blocks, sync lost (FAULTS) and
SLIP.
Available Interfaces: V.24/RS232, V.35/V.11, V.36/V.11, X.21/V.11, RS530;
Transmission rate from 50 to 115200 bps;
Generated patterns: 63, 511, 2047, 4095, 2E15-1, 2E20-1, Mark, Space, ALT M/S,
FOX, USER, 7:1 and 1:7 in the NORMAL and INVERTED modes;
Selection of parity bit, bits/char and stop bits;
Full duplex;
1.3.2 - E1/G.704 Module
TXRX FRAMED MODE: The TSW200E1 can replace a network terminal equipment or
even simulate a network. The TSW200E1 generates a signal internally structured at 2048
kbps following ITU-T Rec. G.704, where the transmitter is independent of the receiver,
allowing signal analysis with PCM frame structures. Some of the characteristics are:
Signal generation with PCM30, PCM30C, PCM31 or PCM31C data structures;
Generated patterns: 7 (2E3-1), 15 (2E4-1), 31 (2E5-1), 63 (2E6-1), 127(2E7-1), 127
LA, 127 LD, 511 (2E9-1), 1023 (2E10-1), 2047 (2E11-1), 2E15-1, 2E17-1, 2E18-
1, 2E20-1 O153, 2E20-1 O151, QRSS, 2E21-1, 2E22-1, 2E23-1, 2E25-1, 2E28-1,
2E29-1, 2E31-1, 2E32-1, all marks (‘1111’), all spaces (‘0000’), ALT M/S
(alternating ‘1s and ‘0s’), Double Alt (‘1100’), 3 in 24, 1 in 16, 1 in 8, 1 in 4, D4
LA, D4 LD, USER, and 7:1 in the NORMAL and INVERTED modes;
Error analysis in one or more timeslots like error bits and blocks, FAS error, CRC
error, E-BIT and code error;
Rate of bits / blocks in error;
Clock SLIP analysis, AIS (Alarm Indicator Signal), frame and multiframe sync losses
analysis. Alarm analysis;
Error analysis like degraded minute count, severe errored seconds, errored seconds,
error-free seconds, available and unavailable seconds following ITU-T Rec.
G.821;
Real-time clock SLIPS counting according to ITU-T Rec. G.822;
Analysis of errors, like block counting error, errored blocks, block background error,
errored seconds, severe errored seconds, available and unavailable seconds,
according to ITU-T Rec. G.826;
Analysis of errors, like errored blocks, errored seconds, severe errored seconds,
seconds available and unavailable following ITU-T Rec. M.2100. According to
that Recommendation, an evaluation is performed to define if a period is accepted,
rejected or inconclusive;
Selection of timeslots to be tested;
Selection of idle code to be transmitted in non-selected channels;
Internal, external or reception-regenerated clock;
G.703 interface impedance: 75 Ω unbalanced, 120 Ω balanced or High impedance (bal
and unbal);
NFAS (Non-Frame Alignment Signal) word Sa bit programming and timeslot #16
signalling word (ABCD bits);
Allows timeslot audio output through loudspeaker;
Insertion of errors (BIT, FAS and CRC);
Wise Telecommunications Industry 4

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