WM8804 Production Data
w
PD Rev 4.1 September 2007
58
REGISTER
ADDRESS
BIT LABEL DEFAULT DESCRIPTION
10h
(read-only)
5:4 CLKACU[1:0] 11 Clock Accuracy of Received Clock
00 = Level II
01 = Level I
10 = Level III
11 = Interface frame rate not matched to
sampling frequency.
0 MAXWL 1 Maximum Audio Sample Word Length
0 = 20 bits
1 = 24 bits
Note: see table in description of bits 3:1 of this
register.
Audio Sample Word Length
000: Word length not indicated
RXWL[2:0] MAXWL==1 MAXWL==0
001 20 bits 16 bits
010 22 bits 18 bits
100 23 bits 19 bits
101 24 bits 20 bits
110 21 bits 17 bits
3:1 RXWL[2:0] 000
All other combinations are reserved and should
not be used.
R17
RXCHAN5
11h
(read-only)
7:4 ORGSAMP
[3:0]
0000 Original Sampling Frequency
Refer to S/PDIF specification (IEC 60958-3) for
full details.
0 CON/PRO 0 Use Of Channel Status Block
0 = Consumer Mode
1 = Professional Mode (not supported by
WM8804).
1 AUDIO_N 0 Linear PCM Identification
0 = S/PDIF transmitted data is audio PCM.
1 = S/PDIF transmitted data is not audio PCM.
2 CPY_N 0 Copyright Information
0 = Transmitted data has copyright asserted.
1 = Transmitted data has no copyright
assertion.
5:3 DEEMPH[2:0] 000 Additional Format Information
000 = Data from Audio interface has no pre-
emphasis.
001 = Data from Audio interface has pre-
emphasis.
All other modes are reserved and should not
be used.
R18
SPDTX1
12h
7:6 CHSTMODE
[1:0]
00 Channel Status Mode
00 = Only valid mode for consumer
applications.
R19
SPDTX2
13h
7:0 CATCODE
[7:0]
00000000 Category Code
Refer to S/PDIF specification (IEC 60958-3) for
full details.
00h indicates “general” mode.