Production Data WM8804
w
PD Rev 4.1 September 2007
61
REGISTER
ADDRESS
BIT LABEL DEFAULT DESCRIPTION
5 AIFRX_LRP 0 Right, left and I
2
S modes – LRCLK polarity and
DSP mode select
1 = invert LRCLK polarity / DSP Mode B
0 = normal LRCLK polarity / DSP Mode A
6 AIF_MS 0 Audio Interface Master/Slave Interface
Select
0 = Slave Mode – LRCLK, BCLK are inputs
1= Master Mode – LRCLK and BCLK are
outputs
2:0 READMUX
[2:0]
000 Status Register Select
Determines which status register is to be read
back:
000 = Interrupt Status Register
001 = Channel Status Register 1
010 = Channel Status Register 2
011 = Channel Status Register 3
100 = Channel Status Register 4
101 = Channel Status Register 5
110 = S/PDIF Status Register
3 CONT 0
Continuous Read Enable
0 = Continuous read-back mode disabled
1 = Continuous read-back mode enabled
4 WITHFLAG 0 ‘With Flags’ Mode Select
0: ‘With Flags’ Mode disabled
1: ‘With Flags’ Mode enabled
6 WL_MASK 0 S/PDIF Receiver Word Length Truncation
Mask
0 = disabled, data word is truncated as
described in Table 44 S/PDIF Receiver
Channel Status Register 5
1 = enabled, data word is not truncated.
R29
SPDRX1
1Dh
7 SPD_192K_EN 1 S/PDIF Receiver 192kHz Support Enable
0 = disabled, S/PDIF receiver maximum
supported sampling frequency is 96kHz
1 = enabled, S/PDIF receiver maximum
supported sampling frequency is 192kHz
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