Xerox 7120 - Card Reader Event Times

Event
.......,'---r------Card reader receives valid read order and reader is in "busy automatic" state.
-l-----cr------ Column 1 arrives at read station. Mode change (EBCDIC to binary) will occur at this
time if rows
1 and 2 are punched.
/Column 80 arrives at read station.
----'------
-1-------- End of card is detectedi card reader signals "channel end" to controlling system. Card
reader returns to "ready" condition (a new S10 can be accepted if no interrupt is pend-
ing) unless the controlling system specifies command chaining, in which case the reader
requests a new read order. New feed cycle begins at this time if new valid read order
is present and reader is still in the "automatic" mode.
-I--------Card arrives at normal stacker if read order specified normal stacking.
-1-------- Card is stacked in normal stacker.
-I---------Card arrives at alternate stacker, if read order specified alternate stacking or stack on
error and error occurred.
--------Card is stacked in alternate stacker.
Notes: @
Card feed cycle is approximately 13 milliseconds if card is picked on first attempt (normal operation),
approximately 45 milliseconds if picked on second attempt, and approximately 77 milliseconds if picked
on third
attempt. If a card does not reach the read station within 96 milliseconds from initiation of feed
cycle, the reader will switch to "not operational", the FEED indicator will light, and the reader drive
motors will turn off. "Unusual end" will be reported to the controlling system. Any other card transport
error (jam) will result in
the same sequence of events.
® The data bytes are transmitted with respect to the reader timing pulses, approximately as follows:
Microseconds
Reader Timing
Pulses
Delay
Data
available
to controller
(clock)
0 200
400
I
I I
lJ
~
Col. 1
U
Col. 2
t
600 800
I
I
U
Col. 3
1000
I
U
t
1200
I
Col. 4
Successive reader timing pulses occur every 644 ± 50 microseconds. The delay pulse width is approxi-
mately 150 microseconds. Column clocks occur in pairs as illustrated. Clock width is 250± 50 micro-
seconds. I indicates controlling system must accept the data before the end of the pulse or data overrun
will
occur. Odd to even clock delay is 10 microseconds. In the EBCDIC mode, one byte is transferred
for
each column. In the binary mode, one byte is transferred for odd columns and two bytes are trans-
ferred for even columns.
Figure
7. Card Reader Event Times (Model 7140)
Programming Considerations 15
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