Xerox OLYMPIA ELECTRONIC COMPACT - Delay Circuit, Reset Circuit; Shift

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3.06

Delay

circuit,

Reset

circuit

(Circuit

Diagram

F)

Since the voltage

UL

+12V

and

then

UC

+SV

are not

soon

available

when

switching

on

the

machine,

a switching-on delay

circuit

is

effected

to

UC

+SV

which

activates the

motors

and

the

hammer

solenoid.

The

CPU

(IC

4)

has

H-level

at

its

pin

33

and

the

NOR

gate

IC

7

at

pin

13

when

the

machine

is switched on.

During

increasing of the

UL

to

+12V,

the

Zener

diode

ZD

1 gives

4.SV

(UL-7.SV)

to

the

base

of

transistor

Tr

3 .

And

its

collector

comes

to L-level

when

the

UL

reaches

10V

or

more.

The

L-level

goes

to the pin

12

of

NOR

gate

IC

7 •

The

L-level is led to the

base

of

Tr

31

from

the output of

IC

7

and

the

Tr

31

is opened.

In

the

meantime

Tr

6 for the driver

circuit

still

keeps

opening.

Then

the capacitor C 2 is charged, the reset input pin 4 of

CPU

comes

to H-level

and

the

CPU

initiates

its

programme.

After the

CPU

has

initiated

the

programme,

the pin

33

comes

to L-level

and

the

pin

13

of

IC

7 also

comes

to L-level.

The

output of

IC

7

comes

to

H-level.

Then

the

transistor

Tr

31

and

Tr

6

open

and

the control

voltage

+SV

is switched through to the driver

circuit.

When

the

machine

is switched off or

when

the

UL

drops

below

9V,

Tr

3

opens

and

pin

12

of

IC

7

comes

to H-level.

The

output

of

IC

7

comes

to L-level.

Then

the transistors

Tr

31

and

Tr

6

open

and

the

control voltage

+SV

for the driver

circuit

is switched

off.

The

switched-through

transistor

(Tr

3)

gives H-level to the

base

of

Tr

4,

which

makes

the pin 4

of

CPU

L-level via the

reset

line.

Then

the reset is effected

by

means

of the capacitor C

2.

3.07 Shift

L

(Circuit

Diagram

F)

The

emitter

of

transistor

Tr

1

has

H-level

from

the

CPU

(IC

4)

via

the pin 9

of

IC

5.

When

pressing the

shift

lock

key,

+SV

goes

to the pin 1 of

IC

7 via

the

cone

1 pin 9

and

the

cone

2

pin

1,

and

the

flip

flop

is

set.

Since the output of

flip

flop

comes

to H-level

and

one

of the

TRA

1

is inverted, L-level

goes

to the

LED

via the

cone

1

pin

10

and

the

LED

lights

on.

In

the

meantime

H-level

goes

to the

keyboard

diode

D G via the collector of

Tr

1

and

cone

2

pin

3,

and

goes

to

the

keyboard

buffer

IC

1 via the

cone

1 pin4.

Thus

the

key

scanning

from

CPU

detects the

shift

lock

key

being

depressed.

When

one

of the

shift

keys

is depressed,

+SV

goes

to the pin 6 of

IC

7 via the

cone

2 pin

1,

and

the

flip

flop

is

reset.

Since

+SV

goes

through the

diode

D 2

and

inverts

one

of the

TRA

1,

L-level

goes

to the

LED

via the

cone

1

pin

10

and

the

LED

lights on.

And

the

key

scanning

from

CPU

detects the

shift

key

being

depressed.

While

the

shift

key

is depressed, the current

keeps

flowing via D 2

to

TRA

1

and

the

LED

keeps

lighting on.

However,

the output of

IC

7

keeps

L-level.

When

the

shift

key

is released, the input

of

the

IC

7

comes

to

L-

level

and

the output is

keeping

its

L-level. Since the base of

Tr

1

comes

to H-level

and

it

opens,

the

LED

has

no

voltage

and

lights

off.

In

the

meantime

L-level

goes

to the

keyboard

diode

D 0 via the

cone

2

pin

3,

and

goes

to the

keyboard

buffer

IC

1 via

9~