• Supply voltage: 1.8V
• Datapath width: 4 bits
• Data rate: variable
For more ash memory details, see the Micron MT25QU01GBBB8E12-0SIT data sheet at the
Micron website.
For conguraon details, see the UltraScale Architecture Conguraon User Guide (UG570). The
detailed FPGA and Flash pin connecons for the feature described in this secon are
documented in the Alveo U200/U250 accelerator card XDC le, referenced in Appendix A: Xilinx
Design Constraints (XDC) File.
USB JTAG Interface
The Alveo accelerator card provides access to the FPGA device via the JTAG interface.
FPGA conguraon is available through the Vivado
®
hardware manager, which accesses the on-
board USB-to-JTAG FT4232HQ bridge device. The micro-AB USB connector on the Alveo U200/
U250 accelerator card PCIe
®
panel/bracket provides external device programming access.
Note: JTAG conguraon is allowed at any me regardless of the FPGA mode pin sengs consistent with
the UltraScale Architecture Conguraon User Guide (UG570).
For more details about the FT4232HQ device, see the FTDI website: hps://www.dichip.com/.
FT4232HQ USB-UART Interface
The FT4232HQ Quad USB-UART provides a UART connecon through the micro-AB USB
connector. The FPGA UART TX/RX (two-wire) connecon is made through the FT4232HQ BD
port. Channel BD implements a 2-wire level-shied TX/RX UART connecon to the FPGA. The
FTDI FT4232HQ data sheet is available on the FTDI website: hps://www.dichip.com/.
PCI Express Endpoint
The Alveo U200/U250 accelerator card implements a 16-lane PCI Express
®
edge connector that
performs data transfers at the rate of 2.5 giga-transfers per second (GT/s) for Gen1, 5.0 GT/s for
Gen2, and 8.0 GT/s for Gen3 applicaons. The -2 speed grade FPGA included with the cards
supports up to Gen3 x16.
Chapter 3: Card Component Description
UG1289 (v1.1.1) November 20, 2019 www.xilinx.com
Alveo U200 and U250 Accelerator Cards 17