Xilinx Alveo U250 User Manual

QSFP28 Module Connectors
The Alveo accelerator cards host two 4-lane small form-factor pluggable (QSFP) connectors that
accept an array of opcal modules. Each connector is housed within a single QSFP cage
assembly.
The QSFP+ connectors are accessible via the I2C interface on the Alveo U200/U250 accelerator
cards. The QSFP connector’s sideband signals are accessible directly from the FPGA. The
MODSELL, RESETL, MODPRSL, INTL, and LPMODE sideband signals are dened in the small
form factor (SFF) specicaons listed below. The components visible through the card PCIe
panel/bracket top to boom are:
• Triple status LEDs
• QSFP0
• QSFP1
• USB
For addional informaon about the quad SFF pluggable (28 Gb/s QSFP+) module, see the
SFF-8663 and SFF-8679 specicaons for the 28 Gb/s QSFP+ at the SNIA Technology Aliates
website: hps://www.snia.org/s/specicaons2.
Each QSFP connector has its own clock generator.
• QSFP0 clock
○ Clock generator: Silicon Labs SI5335A-B06201-GM
○ Output CLK1A/1B: the QSFP0_CLOCK_P/N clock is an AC-coupled LVDS 156.25 MHz
clock wired to the QSFP0 GTY interface
• QSFP1 clock
○ Clock generator: Silicon Labs SI5335A-B06201-GM
○ Output CLK1A/1B: the QSFP1_CLOCK_P/N clock is an AC-coupled LVDS 156.25 MHz
clock wired to the QSFP1 GTY interface
The detailed FPGA and QSFP pin connecons for the feature described in this secon are
documented in the Appendix A: Xilinx Design Constraints (XDC) File.
I2C Bus
The Alveo U200/U250 accelerator cards implement an I2C bus network (the device tree details
are available in the board support package).
Chapter 3: Card Component Description
UG1289 (v1.1.1) November 20, 2019 www.xilinx.com
Alveo U200 and U250 Accelerator Cards 18
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Xilinx Alveo U250 Specifications

General

Brand	Xilinx
Model	Alveo U250
Category	Computer Hardware
Language	English