20 www.xilinx.com AC701 Getting Started Guide
UG967 (v3.0) July 10, 2013
Advanced Bring-up with Base Targeted Reference Design
The intent of this design is to demonstrate a high performance data transfer system using
the PCI Express® x4 GEN2 endpoint with a high performance scatter-gather packet DMA
controller from NorthWest Logic and DDR3 64-bit SODIMM memory operating at
800 Mb/s.
The PCIe® endpoint and DMA controller together are responsible for the movement of
data between a PC and an FPGA. S2C implies data movement from a PC to an FPGA and
C2S implies data movement from an FPGA to a PC. A DDR3 SDRAM (64-bit, 800 Mb/s or
400 MHz) is used for packet buffering — a virtual FIFO layer facilitates the use of DDR3
memory as multiple FIFOs. Additionally, the design provides power monitoring capability
based on a PicoBlaze™ embedded processor.
For software, the design provides 32-bit Linux drivers targeting the Fedora 16 platform
and a graphical user interface (GUI) which controls the tests and monitors the status.
Features
Base Features
This section lists the features of the Targeted Reference Design.
• PCI Express v2.1 compliant x4 endpoint operating at 5Gb/s/lane/direction
• PCIe transaction interface utilization monitor
• MSI & Legacy interrupt support
• Bus Mastering Scatter-gather DMA
• Multichannel DMA
• AXI4-Stream interface for data
• AXI4 interface for register space access
• DMA performance monitor
• Full duplex operation
- Independent transmit and receive channels
• Virtual FIFO layer over DDR3 memory
• Provides 4 channel design (4 FIFOs in DDR3 SODIMM)
Application Features
• PicoBlaze processor-based PVT Monitoring
• Built-in hardware to monitor power by reading the TI UCD90120A power
controller chip included on the AC701 evaluation board
• Built-in hardware to monitor die temperature by way of a Xilinx
Analog-to-Digital Converter
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