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Xilinx Artix-7 FPGA AC701 - Page 33

Xilinx Artix-7 FPGA AC701
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AC701 Getting Started Guide www.xilinx.com 33
UG967 (v3.0) July 10, 2013
Advanced Bring-up with Base Targeted Reference Design
Table 5: Control and Monitoring Interface Components
Callout Component Component Description
1 Led Indicator
Indicates DDR3 calibration information; Green on calibration, red
otherwise
2 Test Option Options to select Loopback, HW Generator, or HW checker
3 Packet size Packet size for the test run with allowed packet size shown as a tool tip
4 Test start/stop control Button to control the start and end of the test
5 DMA statistics
Throughput (Gb/s): DMA payload throughput in gigabits per
second for transmit and receive controllers
DMA Active Time (ns): The time in nanoseconds that the DMA
controller has been active in the last second
DMA Wait Time (ns): The time in nanosecond that the DMA
controller waited for the software to provide more descriptors
BD Errors: Indicates a count of buffer descriptors (BD) that caused a
DMA error as indicated by the error status field in the descriptor
update
BD Short Errors: Indicates a short error in the buffer descriptors in
the transmit direction when the entire buffer specified by length in
the descriptor could not be fetched (Not applicable to the receive
direction)
SW BDs: Indicates the total count of buffer descriptors set up in the
descriptor ring
6 PCIe Transmit (writes in Gb/s)
Reports transmitted (endpoint card to host) throughput as obtained
from the PCIe endpoint hardware performance monitor
7 PCIe Receive (reads in Gb/s)
Reports received (host to endpoint card) throughput as obtained from
the PCIe endpoint hardware performance monitor
8 Message log Text box showing informational messages, warnings, or errors
9 Performance plots
Click this tab to plot the PCIe transactions on the AXI4-Stream interface
and show the payload statistics graph based on the DMA controller
performance monitor
10 Close button Click this button to close the GUI
11 PCIe Endpoint Status
Reports the contents of various PCIe endpoint configuration fields as
reported in the endpoint configuration space
12 Host System’s Initial Credits
Initial flow control credits advertised by the host system after link
training with the endpoint (A value of zero implies infinite flow control
credits)
13 Block diagram button
Click this button to show a case block diagram of each mode currently
running
14 Power statistics
Power in Watt plotted for the VCCINT, GTVCC, VCCAUX, and
VCCBRAM rails
15 Temperature Monitors the current die temperature
Notes:
1. Items 2 through 5 are duplicated for each of the two datapaths.

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