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Xilinx MicroBlaze User Manual

Xilinx MicroBlaze
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UG133 v1.3.1 January 7, 2005 www.xilinx.com MicroBlaze Microcontroller Ref Des User Guide
MicroBlaze Microcontroller Ref Des User Guide
UG133 v1.3.1 January 7, 2005
The following table shows the revision history for this document.
Version Revision
7/22/04 1.0 Initial Xilinx release.
8/27/04 1.1 Edited content; imported new images
11/19/04 1.2 Reconfigured book; added new chapter; incorporated edits
11/30/04 1.3 Reformatted book to consist of chapters for Overview and RefDes1
1/7/05 1.3.1 Made minor non-technical changes only.

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Xilinx MicroBlaze Specifications

General IconGeneral
Architecture32-bit RISC
CacheConfigurable Instruction and Data Cache
CategorySoft Processor Core
Data Width32-bit
Memory Management Unit (MMU)Optional
Floating Point Unit (FPU)Optional
Interrupt ControllerConfigurable
Memory ManagementOptional MMU
ConfigurabilityHighly Configurable
Pipeline Stages3-stage
FPGA IntegrationXilinx FPGAs
Bus InterfacePLB
Debug InterfaceJTAG
Typical Clock SpeedVaries depending on FPGA and configuration (e.g., 100-400+ MHz)
ImplementationSoft core (synthesized logic)
Maximum PerformanceVaries with FPGA and configuration
Debug SupportIntegrated Debug Module

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