Xilinx ML605 User Manual

ML605 Hardware User Guide www.xilinx.com 81
UG534 (v1.2.1) January 21, 2010
NET "DDR3_DQS0_P" LOC = "D12"; ## 12 on J1
NET "DDR3_DQS1_N" LOC = "J12"; ## 27 on J1
NET "DDR3_DQS1_P" LOC = "H12"; ## 29 on J1
NET "DDR3_DQS2_N" LOC = "A14"; ## 45 on J1
NET "DDR3_DQS2_P" LOC = "A13"; ## 47 on J1
NET "DDR3_DQS3_N" LOC = "H20"; ## 62 on J1
NET "DDR3_DQS3_P" LOC = "H19"; ## 64 on J1
NET "DDR3_DQS4_N" LOC = "C23"; ## 135 on J1
NET "DDR3_DQS4_P" LOC = "B23"; ## 137 on J1
NET "DDR3_DQS5_N" LOC = "A25"; ## 152 on J1
NET "DDR3_DQS5_P" LOC = "B25"; ## 154 on J1
NET "DDR3_DQS6_N" LOC = "G28"; ## 169 on J1
NET "DDR3_DQS6_P" LOC = "H27"; ## 171 on J1
NET "DDR3_DQS7_N" LOC = "D30"; ## 186 on J1
NET "DDR3_DQS7_P" LOC = "C30"; ## 188 on J1
NET "DDR3_ODT0" LOC = "F18"; ## 116 on J1
NET "DDR3_ODT1" LOC = "E17"; ## 120 on J1
NET "DDR3_RAS_B" LOC = "L19"; ## 110 on J1
NET "DDR3_RESET_B" LOC = "E18"; ## 30 on J1
NET "DDR3_S0_B" LOC = "K18"; ## 114 on J1
NET "DDR3_S1_B" LOC = "K17"; ## 121 on J1
NET "DDR3_TEMP_EVENT" LOC = "D17"; ## 198 on J1
NET "DDR3_WE_B" LOC = "B17"; ## 113 on J1
##
NET "DVI_D0" LOC = "AJ19"; ## 63 on U38 (thru series R111 47.5 ohm)
NET "DVI_D1" LOC = "AH19"; ## 62 on U38 (thru series R110 47.5 ohm)
NET "DVI_D2" LOC = "AM17"; ## 61 on U38 (thru series R109 47.5 ohm)
NET "DVI_D3" LOC = "AM16"; ## 60 on U38 (thru series R108 47.5 ohm)
NET "DVI_D4" LOC = "AD17"; ## 59 on U38 (thru series R107 47.5 ohm)
NET "DVI_D5" LOC = "AE17"; ## 58 on U38 (thru series R106 47.5 ohm)
NET "DVI_D6" LOC = "AK18"; ## 55 on U38 (thru series R105 47.5 ohm)
NET "DVI_D7" LOC = "AK17"; ## 54 on U38 (thru series R104 47.5 ohm)
NET "DVI_D8" LOC = "AE18"; ## 53 on U38 (thru series R103 47.5 ohm)
NET "DVI_D9" LOC = "AF18"; ## 52 on U38 (thru series R102 47.5 ohm)
NET "DVI_D10" LOC = "AL16"; ## 51 on U38 (thru series R101 47.5 ohm)
NET "DVI_D11" LOC = "AK16"; ## 50 on U38 (thru series R100 47.5 ohm)
NET "DVI_DE" LOC = "AD16"; ## 2 on U38 (thru series R112 47.5 ohm)
NET "DVI_GPIO1_FMC_C2M_PG_LS" LOC = "K9"; ## 18 on U32 (not wired to U38)
NET "DVI_H" LOC = "AN17"; ## 4 on U38 (thru series R113 47.5 ohm)
NET "DVI_RESET_B_LS" LOC = "AP17"; ## 2 on U32 (DVI_RESET_B pin 13 on U38)
NET "DVI_V" LOC = "AD15"; ## 5 on U38 (thru series R114 47.5 ohm)
NET "DVI_XCLK_N" LOC = "AC17"; ## 56 on U38
NET "DVI_XCLK_P" LOC = "AC18"; ## 57 on U38
##
NET "FLASH_A0" LOC = "AL8"; ## 29 on U4, A1 on U27
NET "FLASH_A1" LOC = "AK8"; ## 25 on U4, B1 on U27
NET "FLASH_A2" LOC = "AC9"; ## 24 on U4, C1 on U27
NET "FLASH_A3" LOC = "AD10"; ## 23 on U4, D1 on U27
NET "FLASH_A4" LOC = "C8"; ## 22 on U4, D2 on U27
NET "FLASH_A5" LOC = "B8"; ## 21 on U4, A2 on U27
NET "FLASH_A6" LOC = "E9"; ## 20 on U4, C2 on U27
NET "FLASH_A7" LOC = "E8"; ## 19 on U4, A3 on U27
NET "FLASH_A8" LOC = "A8"; ## 8 on U4, B3 on U27
NET "FLASH_A9" LOC = "A9"; ## 7 on U4, C3 on U27
NET "FLASH_A10" LOC = "D9"; ## 6 on U4, D3 on U27
NET "FLASH_A11" LOC = "C9"; ## 5 on U4, C4 on U27
NET "FLASH_A12" LOC = "D10"; ## 4 on U4, A5 on U27
NET "FLASH_A13" LOC = "C10"; ## 3 on U4, B5 on U27
NET "FLASH_A14" LOC = "F10"; ## 2 on U4, C5 on U27
NET "FLASH_A15" LOC = "F9"; ## 1 on U4, D7 on U27
NET "FLASH_A16" LOC = "AH8"; ## 55 on U4, D8 on U27
NET "FLASH_A17" LOC = "AG8"; ## 18 on U4, A7 on U27
NET "FLASH_A18" LOC = "AP9"; ## 17 on U4, B7 on U27
NET "FLASH_A19" LOC = "AN9"; ## 16 on U4, C7 on U27
NET "FLASH_A20" LOC = "AF10"; ## 11 on U4, C8 on U27

Xilinx ML605 Specifications

General

Brand	Xilinx
Model	ML605
Category	Motherboard
Language	English