Xilinx SmartLynq Plus User Manual

Table 7: HSDP to USB-C Connector Pin Assignments (cont'd)
Pin
USB
Name
HSDP
Name
Description Pin
USB
Name
HSDP
Name
Description
A9 Vbus Vbus Bus power (from host) B4 Vbus Vbus Bus power (from host).
Note: This power is
supplied from the
SmartLynq + Module
when the target is
detected. The power is
used to enable powering
the FTDI part. Note that
only minimal USB2.0
power is supplied.
A10
SSTXn2 - No connection B3 SSRXn2 - No connection
A11 SSTXp2 - No connection B2 SSRXn2 - No connection
A12 GND GND Ground return B1 GND - Ground return
High Speed Differential Pairs
The SmartLynq+ HSDP interface supports standard USB 3.0 cables. As such, high-speed
dierenal pairs (HSDP-TXp/HSDP-TXn and HSDP-RXp/HSDP-RXn) must comply with the
electrical requirements specied in Secon 5.6.1 of the Universal Serial Bus 3.0 Specicaon. The
key electrical requirements are idened in the following table.
Table 8: High Speed Differential Pair Electrical Requirements
Parameter Value
Characteristic impedance 90Ω ± 7Ω
Intra-pair (P-to-N) skew Less than 15 pS per meter
Differential insertion loss
30 AWG: 1.4 dB/m @ 625 MHz, 2.0 dB/m @ 1.25 GHz, 3.00 dB/m @ 2.50 GHz
28 AWG: 1.2 dB/m @ 625 MHz, 1.8 dB/m @ 1.25 GHz, 2.65 dB/m @ 2.50 GHz
Configuration Channel (CC) Connections
The CC lines are used to determine orientaon and power sense. HSDP targets do NOT use the
power from the host, therefore the power sense is ignored. This is how the cable orientaon is
detected from the host:
1. If CC1 is pulled down, the cable is not ipped.
2.
If CC2 is pulled down, the cable is ipped.
The CC connecons are shown in the following gure.
Chapter 9: HSDP Target Interface
UG1514 (v1.0) March 8, 2021 www.xilinx.com
SmartLynq Module+ 32
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Xilinx SmartLynq Plus Specifications

General

Brand	Xilinx
Model	SmartLynq Plus
Category	Network Hardware
Language	English