Xilinx VC707 - Page 104

104 www.xilinx.com VC707 Evaluation Board
UG885 (v1.4) May 12, 2014
Appendix C: Master Constraints File Listing
set_property IOSTANDARD LVCMOS18 [get_ports XADC_GPIO_2]
set_property PACKAGE_PIN BB23 [get_ports XADC_GPIO_3]
set_property IOSTANDARD LVCMOS18 [get_ports XADC_GPIO_3]
#IIC
set_property PACKAGE_PIN AT35 [get_ports IIC_SCL_MAIN_LS]
set_property IOSTANDARD LVCMOS18 [get_ports IIC_SCL_MAIN_LS]
set_property PACKAGE_PIN AU32 [get_ports IIC_SDA_MAIN_LS]
set_property IOSTANDARD LVCMOS18 [get_ports IIC_SDA_MAIN_LS]
set_property PACKAGE_PIN AY42 [get_ports IIC_MUX_RESET_B_LS]
set_property IOSTANDARD LVCMOS18 [get_ports IIC_MUX_RESET_B_LS]
#DDR3
set_property PACKAGE_PIN C29 [get_ports DDR3_RESET_B]
set_property IOSTANDARD LVCMOS15 [get_ports DDR3_RESET_B]
set_property PACKAGE_PIN G19 [get_ports DDR3_CLK1_P]
set_property IOSTANDARD DIFF_SSTL15 [get_ports DDR3_CLK1_P]
set_property PACKAGE_PIN F19 [get_ports DDR3_CLK1_N]
set_property IOSTANDARD DIFF_SSTL15 [get_ports DDR3_CLK1_N]
set_property PACKAGE_PIN H19 [get_ports DDR3_CLK0_P]
set_property IOSTANDARD DIFF_SSTL15 [get_ports DDR3_CLK0_P]
set_property PACKAGE_PIN G18 [get_ports DDR3_CLK0_N]
set_property IOSTANDARD DIFF_SSTL15 [get_ports DDR3_CLK0_N]
set_property PACKAGE_PIN K19 [get_ports DDR3_CKE0]
set_property IOSTANDARD SSTL15 [get_ports DDR3_CKE0]
set_property PACKAGE_PIN J18 [get_ports DDR3_CKE1]
set_property IOSTANDARD SSTL15 [get_ports DDR3_CKE1]
set_property PACKAGE_PIN F20 [get_ports DDR3_WE_B]
set_property IOSTANDARD SSTL15 [get_ports DDR3_WE_B]
set_property PACKAGE_PIN E20 [get_ports DDR3_RAS_B]
set_property IOSTANDARD SSTL15 [get_ports DDR3_RAS_B]
set_property PACKAGE_PIN K17 [get_ports DDR3_CAS_B]
set_property IOSTANDARD SSTL15 [get_ports DDR3_CAS_B]
set_property PACKAGE_PIN H20 [get_ports DDR3_ODT0]
set_property IOSTANDARD SSTL15 [get_ports DDR3_ODT0]
set_property PACKAGE_PIN H18 [get_ports DDR3_ODT1]
set_property IOSTANDARD SSTL15 [get_ports DDR3_ODT1]
set_property PACKAGE_PIN G17 [get_ports DDR3_TEMP_EVENT]
set_property IOSTANDARD SSTL15 [get_ports DDR3_TEMP_EVENT]
set_property PACKAGE_PIN N14 [get_ports DDR3_D0]
set_property IOSTANDARD SSTL15 [get_ports DDR3_D0]
set_property PACKAGE_PIN N13 [get_ports DDR3_D1]
set_property IOSTANDARD SSTL15 [get_ports DDR3_D1]
set_property PACKAGE_PIN L14 [get_ports DDR3_D2]
set_property IOSTANDARD SSTL15 [get_ports DDR3_D2]
set_property PACKAGE_PIN M14 [get_ports DDR3_D3]
set_property IOSTANDARD SSTL15 [get_ports DDR3_D3]
set_property PACKAGE_PIN M12 [get_ports DDR3_D4]
set_property IOSTANDARD SSTL15 [get_ports DDR3_D4]
set_property PACKAGE_PIN N15 [get_ports DDR3_D5]
set_property IOSTANDARD SSTL15 [get_ports DDR3_D5]
set_property PACKAGE_PIN M11 [get_ports DDR3_D6]
set_property IOSTANDARD SSTL15 [get_ports DDR3_D6]
set_property PACKAGE_PIN L12 [get_ports DDR3_D7]
set_property IOSTANDARD SSTL15 [get_ports DDR3_D7]
set_property PACKAGE_PIN K14 [get_ports DDR3_D8]
set_property IOSTANDARD SSTL15 [get_ports DDR3_D8]
set_property PACKAGE_PIN K13 [get_ports DDR3_D9]
set_property IOSTANDARD SSTL15 [get_ports DDR3_D9]
Send Feedback