Xilinx VC707 User Manual

VC707 Evaluation Board www.xilinx.com 85
UG885 (v1.4) May 12, 2014
Appendix C
Master Constraints File Listing
The VC707 board master Xilinx design constraints (XDC) file template provides for
designs targeting the VC707 board. Net names in the constraints listed in this appendix
correlate with net names on the latest VC707 board schematic. Users must identify the
appropriate pins and replace the net names listed here with net names in the user RTL. See
Vivado Design Suite User Guide Using Constraints (UG903) [Ref 11]for more information.
Users can refer to the XDC files generated by tools such as Memory Interface Generator
(MIG) for memory interfaces and Base System Builder (BSB) for more detailed I/O
standards information required for each particular interface. The FMC connectors J35 and
J37 are connected to 1.8V V
cco
banks. Because each user’s FMC card implements
customer-specific circuitry, the FMC bank I/O standards must be uniquely defined by each
customer.
The constraints file listed in this appendix might not be the latest version. Always refer to
the Virtex-7 FPGA VC707 Evaluation Kit product page (www.xilinx.com/vc707
), Docs &
Designs tab, for the latest versions of the FPGA pin constraints files (UCF and XDC files).
Look for "VC707 Master UCF and XDC File".
VC707 Board XDC Listing
#FLASH
set_property PACKAGE_PIN AM36 [get_ports FLASH_D0]
set_property IOSTANDARD LVCMOS18 [get_ports FLASH_D0]
set_property PACKAGE_PIN AN36 [get_ports FLASH_D1]
set_property IOSTANDARD LVCMOS18 [get_ports FLASH_D1]
set_property PACKAGE_PIN AJ36 [get_ports FLASH_D2]
set_property IOSTANDARD LVCMOS18 [get_ports FLASH_D2]
set_property PACKAGE_PIN AJ37 [get_ports FLASH_D3]
set_property IOSTANDARD LVCMOS18 [get_ports FLASH_D3]
set_property PACKAGE_PIN AK37 [get_ports FLASH_D4]
set_property IOSTANDARD LVCMOS18 [get_ports FLASH_D4]
set_property PACKAGE_PIN AL37 [get_ports FLASH_D5]
set_property IOSTANDARD LVCMOS18 [get_ports FLASH_D5]
set_property PACKAGE_PIN AN35 [get_ports FLASH_D6]
set_property IOSTANDARD LVCMOS18 [get_ports FLASH_D6]
set_property PACKAGE_PIN AP35 [get_ports FLASH_D7]
set_property IOSTANDARD LVCMOS18 [get_ports FLASH_D7]
set_property PACKAGE_PIN AM37 [get_ports FLASH_D8]
set_property IOSTANDARD LVCMOS18 [get_ports FLASH_D8]
set_property PACKAGE_PIN AG33 [get_ports FLASH_D9]
set_property IOSTANDARD LVCMOS18 [get_ports FLASH_D9]
set_property PACKAGE_PIN AH33 [get_ports FLASH_D10]
set_property IOSTANDARD LVCMOS18 [get_ports FLASH_D10]
set_property PACKAGE_PIN AK35 [get_ports FLASH_D11]
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Xilinx VC707 Specifications

General

Brand	Xilinx
Model	VC707
Category	Motherboard
Language	English