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Xilinx Virtex-7 FPGA VC7203 Characterization Kit IBERT - Page 34

Xilinx Virtex-7 FPGA VC7203 Characterization Kit IBERT
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34 www.xilinx.com VC7203 IBERT Getting Started Guide
UG847 (v4.0) November 6, 2013
Chapter 1: VC7203 IBERT Getting Started Guide
11. In the new window, select Tools > Run Tcl Script. In the Run Script window, navigate
to add_scm2.tcl in the extracted files and press OK. The SuperClock-2 Module
Design Sources and Constraints are automatically added to the example design
(Figure 1-28).
12. The SuperClock-2 source code now needs to be added to the example ibert wrapper.
Double-click example_ibert_7series_gtx_0 in the Design Sources to open the verilog
code. Add the top level ports from top_scm2.v to the module declaration and
instantiate the top_scm2 module in the example ibert wrapper (Figure 1-29). Click
File > Save File.
X-Ref Target - Figure 1-28
Figure 1-28: Sources after Running add_scm2.tcl
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