Xilinx Virtex-7 FPGA VC7203 User Manual

Virtex-7 FPGA VC7203
Characterization Kit IBERT
Getting Started Guide
Vivado Design Suite 2013.2
UG847 (v3.0) July 10, 2013

Xilinx Virtex-7 FPGA VC7203 Specifications

General

FPGA Family	Virtex-7
Device	XC7VX485T
Transceivers	16
Maximum Transceiver Speed	12.5 Gbps
Transceiver Type	GTX
DSP Slices	2, 800
Block RAM	37, 080 KB
Clock Management Tiles	12
PCIe Gen2/Gen3 Support	Yes
Package	FFG1761

Summary

Chapter 1: VC7203 IBERT Getting Started Guide

Overview

Provides an introduction to setting up the VC7203 board for IBERT demonstrations using Vivado.

Requirements

Lists the hardware and software needed to run the GTX IBERT demonstrations.

Setting Up the VC7203 Board

Details the procedure for physically setting up the VC7203 board, including jumper and module installation.

Extracting the Project Files

Explains how to locate and extract necessary Vivado project files from the SD card or online.

Running the GTX IBERT Demonstration

Outlines the steps to test the GTX IBERT demonstration on the VC7203 board.

Connecting the GTX Transceivers and Reference Clocks

Describes how to connect GTX transceivers and reference clocks using cables and connectors.

Attach the GTX Quad Connector

Details the process of attaching the BullsEye connector to the GTX Quad on the VC7203 board.

GTX Transceiver Clock Connections

Explains how to connect the clock cables to the SuperClock-2 module for GTX reference clocks.

GTX TX/RX Loopback Connections

Guides on setting up TX/RX loopback connections using SMA adapters for GTX transceivers.

Configuring the FPGA

Describes the steps to configure the FPGA using the SD card or Vivado software.

Launching the Vivado Design Suite Software

Instructs on how to start and navigate the Vivado Design Suite for hardware sessions.

Starting the SuperClock-2 Module

Details how to initialize and configure the SuperClock-2 module within the Vivado environment.

Viewing GTX Transceiver Operation

Explains how to monitor GTX transceiver activity and performance in the Serial I/O Analyzer.

Closing the IBERT Demonstration

Provides instructions on how to properly stop and exit the IBERT demonstration.

SuperClock-2 Frequency Table

Lists the addresses and corresponding frequencies for the SuperClock-2 module's ROM.

Creating the GTX IBERT Core

Guides on creating a custom GTX IBERT core using Vivado Design Suite.

Appendix A: Additional Resources

Xilinx Resources

Points to Xilinx support websites for documentation, downloads, and forums.

Solution Centers

Directs users to Xilinx Solution Centers for design assistance and support.

Further Resources

Lists additional websites and documents for the VC7203 kit and its capabilities.

Appendix B: Warranty

Warranty

Outlines the limited warranty terms and conditions for Xilinx development systems.