Xilinx Virtex-7 FPGA VC7203 - Extracting the Project Files; Running the GTX IBERT Demonstration; Connecting the GTX Transceivers and Reference Clocks

VC7203 IBERT Getting Started Guide www.xilinx.com 7
UG847 (v3.0) July 10, 2013
Extracting the Project Files
Extracting the Project Files
The Vivado project files required to run the IBERT demonstrations are located in
vc7203_ibert.zip on the SD card provided with the VC7203 board. They are also
available online (as collection rdf0272_2013_2.zip) at:
www.xilinx.com/vc7203
The ZIP collection also contains two Tcl scripts: add_scm2.tcl and
setup_scm2_156_25.tcl, and seven Vivado probe files: vc7203_q113.ltx,
vc7203_q114.ltx, vc7203_q115.ltx, vc7203_q116.ltx, vc7203_q117.ltx,
vc7203_q118.ltx, and vc7203_q119.ltx. The Tcl scripts are used to help merge the
IBERT and SuperClock-2 source code (described in Creating the GTX IBERT Core, page 26)
and to set up the SuperClock-2 module to run at 156.25 MHz (described in Launching the
Vivado Design Suite Software, page 14). The debug probes are used by Vivado design tools
to properly load the SuperClock-2 VIO core.
To copy the files from the Secure Digital memory card:
1. Connect the Secure Digital memory card to the host computer.
2. Locate the file vc7203_ibert.zip on the Secure Digital memory card.
3. Unzip the files to a working directory on the host computer.
Running the GTX IBERT Demonstration
The GTX IBERT demonstration operates one GTX Quad at a time. This section describes
how to test GTX Quad 115. The remaining GTX Quads are tested following a similar series
of steps.
Connecting the GTX Transceivers and Reference Clocks
Figure 1-1 shows the locations for GTX transceiver Quads 115, 116, 117, and 118 on the
VC7203 board.
Note:
Figure 1-1 is for reference only and might not reflect the current revision of the board.