Xilinx Virtex-7 FPGA VC7203 User Manual

26 www.xilinx.com VC7203 IBERT Getting Started Guide
UG847 (v3.0) July 10, 2013
Chapter 1: VC7203 IBERT Getting Started Guide
Creating the GTX IBERT Core
Vivado Design Suite version 2013.2 or higher is required to rebuild the designs shown
here.
This section provides a procedure to create a single Quad GTX IBERT core with integrated
SuperClock-2 controller. The procedure assumes Quad 113 and 12.5 Gb/s line rate, but
cores for any of the GTX Quads with any supported line rate can be created following the
same series of steps.
For more details on generating IBERT cores, refer to Vivado Design Suite User Guide:
Programming and Debugging (UG908
).
1. Start the Vivado Design Suite.
101 Generic 355.000 114 Generic 420.000 127 Generic 485.000
102 Generic 360.000 115 Generic 425.000
Table 1-2: Si570 and Si5368 Frequency Table (Cont’d)
Address Protocol
Frequency
(MHz)
Address Protocol
Frequency
(MHz)
Address Protocol
Frequency
(MHz)

Xilinx Virtex-7 FPGA VC7203 Specifications

General

FPGA Family	Virtex-7
Device	XC7VX485T
Transceivers	16
Maximum Transceiver Speed	12.5 Gbps
Transceiver Type	GTX
DSP Slices	2, 800
Block RAM	37, 080 KB
Clock Management Tiles	12
PCIe Gen2/Gen3 Support	Yes
Package	FFG1761