Xilinx Virtex-7 FPGA VC7203 User Manual

VC7203 IBERT Getting Started Guide www.xilinx.com 27
UG847 (v3.0) July 10, 2013
Creating the GTX IBERT Core
2. In the Vivado design tools window, click the Manage IP icon, then select Open IP
Catalog (highlighted in Figure 1-20).
3. When the Create a New Customized IP Location dialog window opens (not shown),
click Next.
X-Ref Target - Figure 1-20
Figure 1-20: Initial window, Vivado Design Suite
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Xilinx Virtex-7 FPGA VC7203 Specifications

General

FPGA Family	Virtex-7
Device	XC7VX485T
Transceivers	16
Maximum Transceiver Speed	12.5 Gbps
Transceiver Type	GTX
DSP Slices	2, 800
Block RAM	37, 080 KB
Clock Management Tiles	12
PCIe Gen2/Gen3 Support	Yes
Package	FFG1761