Xilinx Virtex-7 FPGA VC7203 - Page 19

VC7203 IBERT Getting Started Guide www.xilinx.com 19
UG847 (v3.0) July 10, 2013
Running the GTX IBERT Demonstration
4. To view the SuperClock-2 Module VIO core, select the VIO Cores view in the Debug
Probes tab of the Debug Probes window (Figure 1-16).
Note:
The ROM address values for the Si5368 and Si570 devices (that is, si5368_addr[6:0]
and si570_addr[6:0]) are preset to 60 to produce an output frequency of 156.250 MHz. Entering
a different ROM address changes the reference clock(s) frequency. The complete list of
pre-programmed SuperClock-2 frequencies and their associated ROM addresses is provided in
Table 1-2, page 23.
X-Ref Target - Figure 1-15
Figure 1-15: Run Tcl Script...
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