ZC702 and ZVIK Getting Started Guide www.xilinx.com 29
UG926 (v3.0.1) February 12, 2013
Base TRD Key Features
Base TRD Key Features
The PS includes:
• Two ARM Cortex-A9 MPcore processors, each with a 32 KB instruction cache, a 32 KB
data cache, and a NEON™ media processing engine and vector floating-point processor
(VFPv3).
• 512 KB of level 2 cache
• 256 KB of on-chip RAM
• ARM AMBA® AXI interconnect
• Multi-protocol, 32-bit DDR DRAM controller
• Standard peripheral interfaces including USB, Ethernet, UART, I2C, SD MMC, and GPIO
• Clocks and reset for PL
• High bandwidth interconnect between PS and PL
The PL includes:
• Two AXI interconnects, 64-bit wide at 150 MHz
• One AXI interconnect, 32-bit wide at 75 MHz
•AXI VDMA(s)
• A full HD video input (ZVIK) and output interface
• A Sobel accelerator
• Two AXI Performance Monitors
The software includes:
• Xilinx Zynq-7000 AP SoC standard Linux kernel (based on Open Source Linux version
3.x)
• Linux device drivers for TRD-specific IPs.
• A Qt-based Linux application demonstrating the video processing pipeline
• A command line menu-based Linux application demonstrating the video processing
pipeline
Note:
The video demonstration contains the licensed IPs with no timeout.
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